• Korean Journal of Materials Research
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• v.30 no.2
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• pp.99-104
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• 2020

Recent discoveries of ferroelectric properties in ultrathin doped hafnium oxide (HfO₂) have led to the expectation that HfO₂ could overcome the shortcomings of perovskite materials and be applied to electron devices such as Fe-Random access memory (RAM), ferroelectric tunnel junction (FTJ) and negative capacitance field effect transistor (NC-FET) device. As research on hafnium oxide ferroelectrics accelerates, several models to analyze the polarization switching characteristics of hafnium oxide ferroelectrics have been proposed from the domain or energy point of view. However, there is still a lack of in-depth consideration of models that can fully express the polarization switching properties of ferroelectrics. In this paper, a Zr-doped HfO₂ thin film based metal-ferroelectric-metal (MFM) capacitor was implemented and the polarization switching dynamics, along with the ferroelectric characteristics, of the device were analyzed. In addition, a study was conducted to propose an applicable model of HfO₂-based MFM capacitors by applying various ferroelectric switching characteristics models.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.7-13
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• 1998

The VLSI devices of submicron level trend to have a lowering of reliability because of hot carriers by two dimensional influences which are caused by short channel effects and which are not generated in a long channel devices. In order to minimize the two dimensional influences, much research has been made into various types of source/drain structures. MOS typed tunnel transistor with Schottky barrier junctions at source/drain, which has the advantages in fabrication process, downsizing and response speed, has been proposed. The experimental device was fabricated with p type silicon, and manifested the transistor action, showing the unsaturated output characteristics and the high transconductance comparing with that in field effect mode. The results of trial indicate for better performance as follows; high doped channel layer to lower the driving voltage, high resistivity substrate to reduce the leakage current from the substrate to drain.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.