• Annual Conference on Human and Language Technology
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• 2001.10d
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• pp.281-287
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• 2001

번역 메모리(Translation Memory) 시스템이란 기존에 번역된 결과를 담고 있는 대용량의 번역 메모리에서 사용자가 제시한 입력문과 가장 유사한 문장을 검색한 후, 유사도 순으로 결과를 제시하여 이후의 번역 작업을 보다 효율적으로 할 수 있도록 도와주는 시스템을 말한다. 이는 기계 번역 시스템과 비교해 볼때, 보다 실현 가능성이 높은 자연어 처리의 응용 분야라고 할 수 있다. 일반적으로 번역 메모리 시스템에서 핵심이 되는 요소는 번역메모리의 구성과 유사성 척도에 대한 정의라고 할 수 있다. 국외의 경우, 이미 많은 상용 시스템들이 개발되어 번역 작업의 시간 및 비용을 줄이는데 많은 도움을 주고 있지만, 국내의 경우 한국어 번역 메모리의 구성 및 한국어 문장간 유사성 척도 등에 대한 연구가 미흡한 실정이다. 따라서 본 논문에서는 한국어를 대상으로 번역 메모리의 효율적인 구성 방법 및 문장간 유사성 척도에 대한 정의를 내리며, 한국어를 대상으로한 번역 메모리 시스템에 대한 실현 가능성을 논한다.

• Biomolecules & Therapeutics
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• v.14 no.2
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• pp.75-82
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• 2006

Synaptic plasticity, which is a long lasting change in synaptic efficacy, underlies many neural processes like learning and memory. It has long been acknowledged that new protein synthesis is essential for both the expression of synaptic plasticity and memory formation and storage. Most of the research interests in this field have focused on the events regulating transcriptional activation of gene expression from the cell body and nucleus. Considering extremely differentiated structural feature of a neuron in CNS, a neuron should meet a formidable task to overcome spatial and temporal restraints to deliver newly synthesized proteins to specific activated synapses among thousands of others, which are sometimes several millimeters away from the cell body. Recent advances in synaptic neurobiology has found that almost all the machinery required for the new protein translation are localized inside or at least in the vicinity of postsynaptic compartments. These findings led to the hypothesis that dormant mRNAs are translationally activated locally at the activated synapse, which may enable rapid and delicate control of new protein synthesis at activated synapses. In this review, we will describe the mechanism of local translational control at activated synapses focusing on the role of cytoplasmic polyadenylation of dormant mRNAs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.7B
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• pp.818-826
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• 2011

This paper proposes a novel FTL (Flash Translation Layer) algorithm employing sector-level mapping technique based on locality to reduce the number of erase operations in flash memory accesses. Sector-level mapping technique shows higher performance than other mapping techniques, even if it requires a large mapping table. The proposed algorithm reduces the size of mapping table by employing dynamic table update, processes sequential writes by exploiting sequential locality and extracts hot sector in random writes. Experimental results show that the number of erase operations has been reduced by 75.4%, 65.8%, and 10.3% respectively when compared with well-known BAST, FAST and sector mapping algorithms.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.1 no.1
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• pp.23-35
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• 1983

In its global meaning language translation refers to the process whereby a program which is executable in one computer can be executed in another computer directly to obtain the same result. There are four different ways of approaching translation. The first way is translation by a Translator or a Compier, the second way is Interpretation, the third way is Simulation, the last way is Emulation. This paper introduces the M-C Translator which was designed as the first way of translation. The MUSS 80 language (the subsystem of the UNIVAC Solid State 80 S-4 assembly language system) was chosen as the source language which includes forty-three instructions, using the CYBER COMPASS as the object language. The M-C translator is a two pass translator and is a two pas translator and es written in Fortran Extended language. For this M-C Translation, seven COMPASS subroutines and a set of thirty-five macros were prepared. Each executable source instruction corresponds to a macro, so it will be a macro instruction within the object profram. Subroutines are used to retain and handle the source data representation the same way in the object program as in the source system, and are used to convert the decimal source data into the equivalent binary result into the equivalent USS-80digits before and after arithmetic operations. The source instructions can be classified into three categories. First, therd are some instructions which are meaningless in the object system and are therefore unnecessary to translate, and the remaining instructions should be translated. Second, There are some instructions are required to indicate dual address portions. Third, there are Three instructions which have overflow conditions, which are lacking in the remaining instructions. The construction and functions of the M-C Translator, are explained including some of the subroutines, and macros. The problems, difficulties and the method of solving them, and easier features on this translation are analysed. The study of how to save memory and time will be continued.

• The KIPS Transactions:PartD
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• v.17D no.6
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• pp.383-394
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• 2010

Flash memory based SSDs are currently being considered as a promising candidate for replacing hard disks due to several superior features such as shorter access time, lower power consumption and better shock resistance. However, SSDs have different characteristics from hard disk such as difference of unit and time for read, write and erase operation and impossibility for over-writing. Because of these reasons, SSDs have disadvantages on hard disk based systems, so FTL(Flash Translation Layer) is designed to increase SSDs' efficiency. In this paper, we propose an advanced logical address mapping method for increasing SSDs' performance, which is named HAMM(Hybrid Address Mapping Method). HAMM addresses drawbacks of previous block-mapping method and super-block-mapping method and takes advantages of them. We experimented our method on our own SSDs simulator. In the experiments, we confirmed that HAMM uses storage area more efficiently than super-block-mapping method, given the same buffer size. In addition, HAMM used smaller memory than block-mapping method to construct mapping table, demonstrating almost same performance.

• Journal of the Korea Society of Computer and Information
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• v.20 no.5
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• pp.1-12
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• 2015

NAND flash memory has being used for storage systems widely, because it has good features which are low-price, low-power and fast access speed. However, NAND flash memory has an in-place update problem, and therefore it needs FTL(flash translation layer) to run for applications based on hard disk storage. The FTL includes complex functions, such as address mapping, garbage collection, wear leveling and so on. Futhermore, implementation of the FTL on low-power embedded systems is difficult due to its memory requirements and operation overhead. Accordingly, many index data structures for NAND flash memory have being studied for the embedded systems. Overall performances of the index data structures are enhanced by a decreasing of page write counts, whereas it has increased page read counts, as a side effect. Therefore, we propose an index management method using a page mapping log table in $B^+$-Tree based on NAND flash memory to decrease page write counts and not to increase page read counts. The page mapping log table registers page address information of changed index node and then it is exploited when retrieving records. In our experiment, the proposed method reduces the page read counts about 61% at maximum and the page write counts about 31% at maximum, compared to the related studies of index data structures.

• Journal of the Korea Society of Computer and Information
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• v.22 no.4
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• pp.25-32
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• 2017

Recently, the use of NAND flash memory is being increased as a secondary device to displace conventional magnetic disk. NAND flash memory, as one among non-volatile memories, has many advantages such as low power, high reliability, low access latency, and so on. However, NAND flash memory has disadvantages such as erase-before-write, unbalanced operation speed, and limited P/E cycles, unlike conventional magnetic disk. To solve these problems, NAND flash memory mainly adopted FTL (Flash Translation Layer). In particular, garbage collection technique in FTL tried to improve the system lifetime. However, previous garbage collection techniques have a sensitive property of the system lifetime according to write pattern. To solve this problem, we propose BSGC (Balanced Selection-based Garbage Collection) technique. BSGC efficiently selects a victim block using all intervals from the past information to the current information. In this work, SFL (Search First linked List), as the proposed block allocation policy, prolongs the system lifetime additionally. In our experiments, SFL and BSGC prolonged the system lifetime about 12.85% on average and reduced page migrations about 22.12% on average. Moreover, SFL and BSGC reduced the average response time of 16.88% on average.

• Journal of the Korea Society of Computer and Information
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• v.20 no.4
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• pp.1-10
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• 2015

NAND flash systems require deletion operation and do not support in-place update, so the storage systems should use Flash Translation Layer (FTL). However, there are a lot of memory consumptions using mapping table in the FTL, so recently, many studies have been proposed to resolve mapping table overhead. These studies try to solve update propagation problem in the nand flash system which does not use mapping table. In this paper, we present a novel index structure, called CL-Tree(Cache List Tree), to solve the update propagation problem. The proposed index structure reduces write operations which occur for an update propagation, and it has a good performance for search operation because it uses multi-list structure. In experimental evaluation, we show that our scheme yields about 173% and 179% improvement in insertion speed and search speed, respectively, compared to traditional B+tree and other works.

• Journal of Digital Contents Society
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• v.14 no.1
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• pp.51-57
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• 2013

Storage device based on Flash Memory have many attractive features such as high performance, low power consumption, shock resistance, and low weight, so they replace HDDs to a certain extent. An Storage device based on Flash Memory has FTL(Flash Translation Layer) which emulate block storage devices like HDDs. A garbage collection, one of major functions of FTL, effects highly on the performance and the lifetime of devices. However, there is no de facto standard for new garbage collection algorithms. To solve this problem, we propose File Clustering Algorithm. File Clustering Algorithm respect to update page from same file at the same time. So, these are clustered to same block. For this mechanism, We propose Page Allocation Policy in FTL and use MIN-MAX GAP to guarantee wear leveling. To verify the algorithm in this paper, we use TPC Benchmark. So, The performance evaluation reveals that the proposed algorithm has comparable result with the existing algorithms(No wear leveling, Hot/Cold) and shows approximately 690% improvement in terms of the wear leveling.

• Korean Journal of Cognitive Science
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• v.9 no.1
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• pp.47-60
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• 1998

The study was designed to investigate implicit and explicit memory effec representations of bilinguals. Hierarchical model of bilingual information processing word naming and translation tasks in the context of semantically categorized or rar Experiments 1 and 2, bilinguals first viewed stimulus words and performed naming or tr then implicit and explicit memory tasks. In experiment I, word recognition times(exp were significantly faster for semantic category condition than random category condi naming task and lexical decision taskOmplicit memory task)showed no difference in e experiment 2, naming task and exlicit memory task showed categorization effect but fOWE a and implcit memory task showed no categorization effect. These findings support the which posits that memory representations of bilinguals are composed of two independer a and one common conceptual store.