• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.333-337
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• 2007

Flash Translation Layer(FTL) which enables NAND Flash memory-based storage system to be used as a block device is designed considering only characteristics of NAND Flash memory. However, since FTL precesses I/O requests which survived against buffer replacement algorithm, FTL algorithm has tight relationship with buffer replacement algorithm. Therefore, if we do not consider both FTL and buffer replacement algorithms, it is difficult to predict the actual I/O performance of the computer systems that have Flash memory-based storage system. The necessity of FTL and buffer replacement algorithm co-design arises here. In this work, we implemented I/O performance evaluation tool, IPSiNS, which simulates both the buffer replacement and FTL algorithms, simultaneously.

• Journal of the Korea Society of Computer and Information
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• v.15 no.8
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• pp.23-30
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• 2010

Flash memory is non-volatile and can retain data even after system is powered off. Besides, it has many other features such as fast access speed, low power consumption, attractive shock resistance, small size, and light-weight. As its price decreases and capacity increases, the flash memory is expected to be widely used in consumer electronics, embedded systems, and mobile devices. Flash storage systems generally adopt a software layer, called FTL. In this research, we proposed a new FTL mechanism for overcoming the major drawback of conventional block mapping algorithm. In addition to the block mapping table, a index block mapping table with a small size is used to indicate sector location. The proposed indexed block mapping algorithm by adding a small size. By the simulation result, the proposed FTL provides an enhanced speed than a conventional hybrid mapping algorithm by around 45% in average, and the requirement of mapping memory is also reduced by around 12%.

• Journal of KIISE
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• v.42 no.4
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• pp.434-441
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• 2015

Next generation memory technologies, which we denote as 'new memory', have both non-volatile and byte addressable properties. These characteristics are expected to bring changes to the conventional computer system structure. In this paper, we propose a fast boot technique for hybrid main memory architectures that have both new memory and DRAM. The key technique used for fast booting is write-tracking. Write-tracking is used to detect and manage modified data detection and involves setting the kernel region to read-only. This setting is used to trigger intentional faults upon modification requests. As the fault handler can detect the faulting address, write-tracking makes use of the address to manage the modified data. In particular, in our case, we make use of the MMU (Memory Management Unit) translation table. When a write occurs to the boot completed state, write-tracking preserves the original state of the modified address of the kernel region to a particular location, and execution continues. Upon booting, the fast booting process restores the preserved data to the original kernel region allowing rapid system boot-up. We develop the fast booting technique in an actual embedded board equipped with new memory. The boot time is reduced to less than half a second compared to around 15 seconds that is required for the original system.

• Journal of Digital Contents Society
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• v.13 no.1
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• pp.75-81
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• 2012

SSDs(Solid State Drives) have many attractive features such as high performance, low power consumption, shock resistance, and low weight, so they replace HDDs to a certain extent. An SSD has FTL(Flash Translation Layer) which emulate block storage devices like HDDs. A garbage collection, one of major functions of FTL, effects highly on the performance and the lifetime of SSDs. However, there is no de facto standard for new garbage collection algorithms. To solve this problem, we propose trace driven offline optimal algorithms for garbage collection of FTL. The proposed algorithm always guarantees minimal number of erase operation. In addition, we verify our proposed algorithm using TPC trace.

• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.1
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• pp.9-16
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• 2020

Recently, the capacity of SSD has been increasing rapidly due to the improvement of flash memory density. To take full advantage of these SSDs, first of all, FTL's prompt adaptation is necessary. The FTL is a translation layer existing in SSDs to overcome the drawback of the SSD that cannot be modified in place, and has garbage collection and caching functions in addition to the map table management function. In this study, we focus on caching function, compare and analyze the cache implementation methodologies, and propose improved methods. Typical cache implementations divide the cache into groups, manage and retrieve the caches in the group as a linked list. Thus, searches are made in the order of the linked list. In contrast, we propose a method of sequential searching using the search area group of a cache registered in the map table regardless of the linked list and cache group. Experimental results show that the proposed method has a 2.5 times improvement over the conventional method.

• Electronics and Telecommunications Trends
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• v.35 no.4
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• pp.91-102
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• 2020

Recently, generative adversarial networks (GANs) is a field of research that has rapidly emerged wherein many studies conducted shows overwhelming results. Initially, this was at the level of imitating the training dataset. However, the GAN is currently useful in many fields, such as transformation of data categories, restoration of erased parts of images, copying facial expressions of humans, and creation of artworks depicting a dead painter's style. Although many outstanding research achievements have been attracting attention recently, GANs have encountered many challenges. First, they require a large memory facility for research. Second, there are still technical limitations in processing high-resolution images over 4K. Third, many GAN learning methods have a problem of instability in the training stage. However, recent research results show images that are difficult to distinguish whether they are real or fake, even with the naked eye, and the resolution of 4K and above is being developed. With the increase in image quality and resolution, many applications in the field of design and image and video editing are now available, including those that draw a photorealistic image as a simple sketch or easily modify unnecessary parts of an image or a video. In this paper, we discuss how GANs started, including the base architecture and latest technologies of GANs used in high-resolution, high-quality image creation, image and video editing, style translation, content transfer, and technology.

• Annual Conference on Human and Language Technology
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• 2009.10a
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• pp.50-55
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• 2009

현재, 자동번역의 도메인은 응용 프로그램의 요구에 따라, 점차 문어체에서 대화체(spoken language)로 옮겨가고 있는 추세이다. 본 논문은 대화체가 지니는 특성을 자동번역 시스템을 구성하는 각 모듈별 및 지식 관점에서 분석하였다. 특성 분석을 기반으로 하여, 본 논문에서는 여행 영역을 대상으로 하는 대화체 자동번역시스템의 특화를 수행하였다. 대화체 자동번역을 위한 새로운 지식으로 구조화 번역메모리(Translation Memory)가 도입되었으며, 시스템을 구성하는 각 모듈별로 대화체 특화가 이루어졌다. 또한 기존의 문어체용 기구축 패턴 등이 정비되었으며, 고빈도 대화체 표현에 대한 신규 패턴이 도입되었다. 제안하는 방법의 검증을 위해 수동평가를 수행하였으며, 그 결과, 영한 대화체 자동번역에 있어서 번역률 향상이 있었다.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.836-840
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• 2009

Many researchers have studied flash memory in order to replace hard disk storages. Many FTL algorithms have been proposed to overcome physical constraints of flash memory such as erase-before-write, wear leveling, and poor write performance. Therefore, these constraints should be considered for testing FTL algorithms and the performance evaluation of flash memory. As doing the experiments, we suffer from several problems with costs and settings in experimental configuration. When we, for example, replay the traces of Oracle to evaluate the I/O performance with flash memory, it is hard to extract exact traces of I/O operations in Oracle. Since there are only write operations in the log, it is impossible to gather read operations. In MySQL and SQLite, we can gather the read operations by changing I/O functions in the source codes. But it is not easy to search for the exact points about I/O and even if we can find out the points, we might get wrong results depending on how we modify source codes to get I/O traces. The FlaSim proposed in this paper removes the difficulties when we evaluate the performance of FTL algorithms and flash memory. Our Linux drivers emulate the flash memory as a hard disk. And we can easily obtain the usage statistics of flash memory such as the number of write, read, and erase operations. The FlaSim can be gracefully extended to support the additional modules implemented by novel algorithms and ideas. In this paper, we describe the structure of FTL emulator, development tools and operating methods. We expect this emulator to be helpful for many experiments and research with flash memory.

• Journal of Korean Medical classics
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• v.23 no.1
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• pp.143-161
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• 2010

The "Dong-uibogam(東醫寶鑑)" is a Korean medical book which represents the Korean Oriental Medicine and compiled by the royal physician, Heo Jun. It was placed on UNESCO's Memory of the World Programme in the year of 2009. It has been translated and published in Korean 7 times so far, and most of them depended on the liberal translation. This study has a purpose to investigate the Korean version in the view of Chinese writing grammar, and the results can be concluded as follows ; 1. The Korean version shows insufficient translation of individual morpheme in the sentence which has the prepositions with the pronouns or the conjunctions. 2. Most of the versions failed to translate the syntax properties of the demonstrative pronoun; '之' and '其'. 3. Some of the versions are not successful in the understanding of the constituent of sentence correctly. 4. Many of the adverbial phrases are not translated, which is the constituent of modifier in the sentence. 5. Some sentences are mistranslated by the paragraphs. 6. Some of them failed to understand the significances of the vocabularies.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.4
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• pp.232-243
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• 2002

There are many methods for improving TLB (translation lookaside buffer) performance, such as increasing the number of entry in TLB, supporting large page or multiple page sizes. The best way is to support multiple page sizes, but any operating system doesn't support multiple page sizes in user mode. So, we propose the new structure of TLB supporting two pages to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. we propose a new TLB structure supporting two page sizes dynamically and selectively for high performance and low cost design without any operating system support. For high performance, a promotion-TLB is designed by supporting two page sizes. Also in order to attain low power consumption, a banked-TLB is constructed by dividing one fully associative TLB space into two sub-fully associative TLBs. These two banked-TLB structures are integrated into a banked-promotion TLB as a low power and high performance TLB structure for embedded processors. According to the results of comparison and analysis, a similar performance can be achieved by using fewer TLB entries and also power consumption can be reduced by around 50% comparing with the fully associative TLB.