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An Efficient Task Assignment Algorithm for Heterogeneous Multi-Computers (이종의 다중컴퓨터에서 태스크 할당을 위한 효율적인 알고리즘)

  • Seo, Kyung-Ryong;Yeo, Jeong-Mo
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.5
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    • pp.1151-1161
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    • 1998
  • In this paper, we are considering a heterogeneous processor system in which each processor may have different performance and reliability characteristics. In other to fully utilize this diversity of processing power it is advantageous to assign the program modules of a distributed program to the processors in such a way that the execution time of the entire program is minimized. This assignment of tasks to processors to maximize performance is commonly called load balancing, since the overloaded processors can perform their own processing with the performance degradation. For the task assignment problem, we propose a new objective function which formulates this imbalancing cost. Thus the task assignment problem is to be carried out so that each module is assigned to a processor whose capabilities are most appropriate for the module, and the total cost is minimized that sum of inter-processor communication cost and execution cost and imbalance cost of the assignment. To find optimal assignment is known to be NP-hard, and thus we proposed an efficient heuristic algorithm with time complexity $O(n^2m)$ in case of m task modules and n processors.

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Implement and Experiment of Efficient Off-Chain (단방향 해시 함수를 활용한 효율적인 Off-chain Payment Channel 구현 및 실험)

  • Kim, Sun Hyoung;Jeong, Jae Yeol;Jeong, Ik Rae
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.29 no.6
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    • pp.1413-1424
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    • 2019
  • Cryptocurrency has limitations to be used as an actual payment method due to the scalability problem of the blockchain consensus protocol, and various off-chain solutions to solve these limitations are being studied. In this paper, we design an efficient off-chain payment channel using one-way hash function and implement the designed payment channel using Ethereum smart contract. In addition, the experiment was conducted to measure and analyze execution time and cost for each method by deploying it in the same environment as the previously implemented plasma MVP. As a result, compared with plasma MVP, the proposed solution was able to reduce the total cumulative time by about 34% and reduce the overall execution cost by about 41%.

A Hardware Cache Prefetching Scheme for Multimedia Data with Intermittently Irregular Strides (단속적(斷續的) 불규칙 주소간격을 갖는 멀티미디어 데이타를 위한 하드웨어 캐시 선인출 방법)

  • Chon Young-Suk;Moon Hyun-Ju;Jeon Joongnam;Kim Sukil
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.11
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    • pp.658-672
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    • 2004
  • Multimedia applications are required to process the huge amount of data at high speed in real time. The memory reference instructions such as loads and stores are the main factor which limits the high speed execution of processor. To enhance the memory reference speed, cache prefetch schemes are used so as to reduce the cache miss ratio and the total execution time by previously fetching data into cache that is expected to be referenced in the future. In this study, we present an advanced data cache prefetching scheme that improves the conventional RPT (reference prediction table) based scheme. We considers the cache line size in calculation of the address stride referenced by the same instruction, and enhances the prefetching algorithm so that the effect of prefetching could be maintained even if an irregular address stride is inserted into the series of uniform strides. According to experiment results on multimedia benchmark programs, the cache miss ratio has been improved 29% in average compared to the conventional RPT scheme while the bus usage has increased relatively small amount (0.03%).

Robust Deadbeat Current Control Method for Three-Phase Voltage-Source Active Power Filter

  • Nishida, Katsumi;Ahmed, Tarek;Nakaoka, Mutsuo
    • Journal of Power Electronics
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    • v.4 no.2
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    • pp.102-111
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    • 2004
  • This paper is concerned with a deadbeat current control implementation of shunt-type three-phase active power filter (APF). Although the one-dimensional deadbeat control method can attain time-optimal response of APF compensating current, one sampling period is actually required fur its settling time. This delay is a serious drawback for this control technique. To cancel such a delay and one more delay caused by DSP execution time, the desired APF compensating current has to be predicted two sampling periods ahead. Therefore an adaptive predictor is adopted for the purpose of both predicting the control error of two sampling periods ahead and bringing the robustness to the deadbeat current control system. By adding the adaptive predictor output as an adjustment term to the reference value of half a source voltage period before, settling time is made short in a transient state. On the other hand, in a steady state, THD (total harmonic distortion) of the utility grid side AC source current can be reduced as much as possible, compared to the case that ideal identification of controlled system could be made.

The Cardinality Constrained Multi-Period Linear Programming Knapsack Problem (선수제약 다기간 선형계획 배낭문제)

  • Won, Joong-Yeon
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.38 no.4
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    • pp.64-71
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    • 2015
  • In this paper, we present a multi-period 0-1 knapsack problem which has the cardinality constraints. Theoretically, the presented problem can be regarded as an extension of the multi-period 0-1 knapsack problem. In the multi-period 0-1 knapsack problem, there are n jobs to be performed during m periods. Each job has the execution time and its completion gives profit. All the n jobs are partitioned into m periods, and the jobs belong to i-th period may be performed not later than in the i-th period, i = 1, ${\cdots}$, m. The total production time for periods from 1 to i is given by $b_i$ for each i = 1, ${\cdots}$, m, and the objective is to maximize the total profit. In the extended problem, we can select a specified number of jobs from each of periods associated with the corresponding cardinality constraints. As the extended problem is NP-hard, the branch and bound method is preferable to solve it, and therefore it is important to have efficient procedures for solving its linear programming relaxed problem. So we intensively explore the LP relaxed problem and suggest a polynomial time algorithm. We first decompose the LP relaxed problem into m subproblems associated with each cardinality constraints. Then we identify some new properties based on the parametric analysis. Finally by exploiting the special structure of the LP relaxed problem, we develop an efficient algorithm for the LP relaxed problem. The developed algorithm has a worst case computational complexity of order max[$O(n^2logn)$, $O(mn^2)$] where m is the number of periods and n is the total number of jobs. We illustrate a numerical example.

A Case Study on Kinematical Traits Analysis when Performing of Uchimatia(inner thigh reaping throw) by Posture and Voluntary Resistance Levels(VRL) of Uke in Judo[ I ] (유도 허벅다리걸기 기술발휘 시 받기의 자세와 저항수준에 따른 운동학적 특성 분석 사례연구[ I ])

  • Kim, Eui-Hwan;Yoon, Hyun;Kim, Sung-Sup
    • Korean Journal of Applied Biomechanics
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    • v.14 no.3
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    • pp.235-257
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    • 2004
  • The purpose of this study was to analyze the kinematical traits variables when performing Uchimata(inner thigh reaping throw) by Voluntary Resistance Levels(VRL) and two postures of Uke in Judo. The subjects, who were one male judoka(YH) for 1992 Barcelona Olympic Games, and one male trainee Y. I. University representative member(SDK) and were filmed on two S-VHS 16 mm video cameras(60fields/sec.), that posture of Uke were Shizenhontai(straight defensive posture) and Jigohontai(straight natural posture), VRL of Uke were 0% and 100%. The kinematical variables were temporal(total time-required: TR), potures and COG variables etc., The data of this study collection were digitized by SIMI Motion Program computed the mean values and the standard deviation calculated for each variables. When performing according to each posture and VRL, from the data analysis and discussion, the conclusions were as follows : 1. Temporal variables total time-required(TR) when performing Uchimata was shown the shortest time YH than SDK by each posture and VRL. TR of each posture were shown the shorten trends or equal in DP by lower than NP, In existence and / or nonexistence of VRL was shown the shorten trends in VRL 0% than 100% of Uke. 2. Posture variables : In attacking right knee angle, YH was performing flexion($147{\rightarrow}103degree$) from Tsukuri(set-up) to Kake(execution) in regardless of postures and VRLs, SDK was performing not exchange extension and flexion in VRL 100%, and extension($120{\rightarrow}142degree$) in VRL 0%, respectively. In supporting left hee angle, YH was performing extension($119{\rightarrow}163degree$) from Tsukuri(set-up) to Kake(at(execution) in regardless of postures and VRLs, SDK extension($93{\rightarrow}139degree$), respectively. In attacking right hip angle, from Tsukuri to Kake, YH was performing extension($133{\rightarrow}169degree$), except in VRL 0%($156{\rightarrow}137degree$) NP, SDK was performing flexion($159{\rightarrow}126degree$) accept in VRL 100%($149{\rightarrow}152degree$) NP, In left hip angle, from Tsukuri to Kake, YH was performing flexion NP(70, 50degree) more than DP(27, 57degree), SDK was performing flexion DP(73, 52degree) more than NP(34, 20degree). 3. COG variables : When performing Uchimata, vertical COG variables was shown YH(:$2{\sim}8cm$), SDK(:$15{\sim}24cm$) lower than Uke's COG level position, in existence and / or nonexistence of postures and VRL, during Kake as maximum force point of throwing techniques in Judo.

A Threshold Controller for FAST Hardware Accelerator (FAST 하드웨어 가속기를 위한 임계값 제어기)

  • Kim, Taek-Kyu;Suh, Yong-Suk
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.11
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    • pp.187-192
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    • 2014
  • Various researches are performed to extract significant features from continuous images. The FAST algorithm has the simple structure for arithmetic operation and it is easy to extraction the features in real time. For this reason, the FPGA based hardware accelerator is implemented and widely applied for the FAST algorithm. The hardware accelerator needs the threshold to extract the features from images. The threshold is influenced not only the number of extracted features but also the total execution time. Therefore, the way of threshold control is important to stabilize the total execution time and to extract features as much as possible. In order to control the threshold, this paper proposes the PI controller. The function and performance for the proposed PI controller are verified by using test images and the PI control logic is designed based on Xilinx Vertex IV FPGA. The proposed scheme can be implemented by adding 47 Flip Flops, 146 LUTs, and 91 Slices to the FAST hardware accelerator. This proposed approach only occupies 2.1% of Flip Flop, 4.4% of LUTs, and 4.5% of Slices and can be regarded as a small portion of hardware cost.

The Comparative Study of Software Optimal Release Time Based on Extreme Distribution Property (극값분포 특성에 근거한 소프트웨어 최적 방출시기에 관한 비교)

  • Kim, Hee-Cheul
    • Journal of IKEEE
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    • v.15 no.1
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    • pp.43-48
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    • 2011
  • Decision problem called an optimal release policies, after testing a software system in development phase and transfer it to the user, is studied. The infinite failure non-homogeneous Poisson process models presented and propose an optimal release policies of the life distribution applied extreme distribution which used to find the minimum (or the maximum) of a number of samples of various distributions. In this paper, discuss optimal software release policies which minimize a total average software cost of development and maintenance under the constraint of satisfying a software reliability requirement. In a numerical example, extreme value distribution as another alternative of existing the Poisson execution time model and the log power model can be verified using inter-failure time data.

Maximal Parallelism in Local Microprogram (Local Microprogram의 병렬 수행의 최대화)

  • 조영일;임인칠
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.21 no.3
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    • pp.13-18
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    • 1984
  • This paper suggests an algorithm which can perform microoperations (MO'S) in parauel by considering concurrency of MO'S and resource allocation in horizontal microprogams. The algorithm can be obtained the result which reduces execution time and the space of control memory in microprogrammed digital systems by minimizing the total number of microinctructions by combining MO'5, which can be performed in paiallel by assigning a weight to each MO in the SLM (straight line microprogram), into a microinstruction.

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Dynamic Task Scheduling Via Policy Iteration Scheduling Approach for Cloud Computing

  • Hu, Bin;Xie, Ning;Zhao, Tingting;Zhang, Xiaotong
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.3
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    • pp.1265-1278
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    • 2017
  • Dynamic task scheduling is one of the most popular research topics in the cloud computing field. The cloud scheduler dynamically provides VM resources to variable cloud tasks with different scheduling strategies in cloud computing. In this study, we utilized a valid model to describe the dynamic changes of both computing facilities (such as hardware updating) and request task queuing. We built a novel approach called Policy Iteration Scheduling (PIS) to globally optimize the independent task scheduling scheme and minimize the total execution time of priority tasks. We performed experiments with randomly generated cloud task sets and varied the performance of VM resources using Poisson distributions. The results show that PIS outperforms other popular schedulers in a typical cloud computing environment.