• Korean Journal of Materials Research
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• v.1 no.4
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• pp.191-197
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• 1991

The surface roughnesses of titanium silicide films and the diffusion behaviours of dopants in single crystal and polycrystalline silicon substrates durng titanium silicide formation by rapid thermal annealing(RTA) of sputter deposited Ti-filicide film from the composite $TiSi_{2.6}$ target were investigated by the secondary ion mass spectrometry(SIMS), a four-point probe, X-ray diffraction, and surface roughness measurements. The as-deposited films were amorphous but film prepared on single silicon substrate crystallized to the orthorhombic $TiSi_2$(C54 structure) upon rapid thermal annealing(RTA) at $800^{\circ}C$ for 20sec. There was no significant out-diffusion of dopants from both single crystal and polycrystalline silicon substrate into titanum silicide layers during annealing. Most of the implanted dopants piled up near the titanium silicide/silicon interface. The surface roughnesses of titanium silicide films were in the range between 16 and 22nm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.252-258
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• 2013

In this paper, a thermally stable nickel silicide technology using the co-sputtering of nickel and titanium atoms capped with TiN layer is proposed for nano-scale metal oxide semiconductor field effect transistor (MOSFET) applications. The effects of the incorporation of titanium ingredient in the co-sputtered Ni layer are characterized as a function of Ti sputtering power. The difference between the one-step rapid thermal process (RTP) and two-step RTP for the silicidation process has also been studied. It is shown that a certain proportion of titanium incorporation with two-step RTP has the best thermal stability for this structure.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2005.11a
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• pp.103-103
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• 2005

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.5
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• pp.399-405
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• 1990

Rapid Thermal Process(RTP) has been used to precisely control and study the reaction rate for the formation of refractory titanuium silicide. Samples were prepared by sputtering deposition layer of titanium on n-type, poly-deposit silicon wafers. The process were then sujected to a matrix of rapid time-temperature profile under nitrgen, argon gas ambient to precisely control the silicide formation. Reacted films were analyzed by the sheet resistance measursrement, SEM, ASR and X-ray diffraction. Results were shown that the resistivity of the silicide films are below 20u-cm and the thickness of silicide films are about two times than that of as-deposited titanium films. Silicidation ambient was likely to happen at the same tamperature-time condition for argon and nitrogen gas.

• 연구논문집
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• s.29
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• pp.163-171
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• 1999

A new titanium alloy system. Ti-xFe-ySi (x,y=0-4 wt%). was designed and characterized with the point at low cost and high strength for casting applications. Fe improved room and elevated temperature mechanical properties owing to solid solution hardening and beta phase stabilization. Si yielded titanium silicides and Si addition over 1 wt% resulted in poor ductility due to coarse silicide chains at prior beta boundaries. The optimum composition was found to be Ti-4Fe-(0.5-1)Si in the viewpoint of tensile strength and ductility which are comparable to the Ti-6Al-4V. The metal-mould reaction was also examined for Ti-xFe and Ti-xSi binary alloy system. The thickness of surface reaction layer w as not affected significantly with Fe content, while it was decreased with Si content. In the Ti-4Si alloy, no reaction layer was found. The depth of surface hardening layer was about $200\mum$ regardless of the mould materials.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.60-63
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• 2000

We have investigated the relationship between electrical and morphological properties of titanium silicide films. In this study, the C54 titanium silicides were formed by using high temperature sputtering and one-step annealing. From the measurement of electrical and morphological properties, a smooth surface and a relaxed roughness were observed for the titanium silicide film fabricated by high temperature sputtering. And it seems that the previous effect could improve electrical properties.

• Korean Journal of Materials Research
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• v.12 no.11
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• pp.883-888
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• 2002

We investigated the void formation in composite-titanium silicide($TiSi_2$) process. We varied the process conditions of polycrystalline/amorphous silicon substrate, composite $TiSi_2$ deposition temperature, and silicidation annealing temperature. We report that the main reason for void formation is the mass transport flux discrepancy of amorphous silicon substrate and titanium in composite layer. Sheet resistance in composite $TiSi_2$ without patterns is mainly affected by silicidation rapid thermal annealing (RTA) temperature. In addition, sheet resistance does not depend on the void defect density. Sheet resistance with sub-0.5 $\mu\textrm{m}$ patterns increase abnormally above $850^{\circ}C$ due to agglomeration. Our results imply that $sub-750^{\circ}C$ annealing is appropriate for sub 0.5 $\mu\textrm{m}$ composite X$sub-750_2$ process.

• Journal of Powder Materials
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• v.12 no.6 s.53
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• pp.447-452
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• 2005

The synthesis and consolidation of titanium silicide by electro-discharge-sintering has been investigated. As-received Ti powder was in flaky shape and the mean particle size was $45.0{\mu}m$, whereas the mean particle size of the pre-milled Si powder with angular shape was $8.0{\mu}m$. Single pulse of 2.5 to 5.0 kJ/0.34g-elemental Ti and pre-milled Si powder mixture with the composition of $Ti-37.5at.\%$ Si was applied using $300{\mu}F$ capacitor. The solid with $Ti_5Si_3$ phase has been successfully fabricated by the discharge with the input energy more than 2.5kJ in less than $129{\mu}sec.$ Hv values were found to be higher than $1000kgf/mm^2$. The formation of $Ti_5Si_3$ occurred through a fast solid state diffusion reaction.