• 한국재료학회지
• /
• 제1권4호
• /
• pp.191-197
• /
• 1991

Composite $TiSi_{2.6}$ target으로 부터 Ti-silicide를 형성시 단결정 Si기판과 다결정 Si내의 dopant의 확산 거동, 그리고 Ti-silicide 박막의 표면 거칠기를 secondary ion mass spectrometry (SIMS), 4-point probe, X-선 회절 분석, 표면 거칠기 측정을 통해 조사하였다. X-선 회절 분석결과 중착된 직후의 중착막은 비정질이었고, 단결정 Si기판에 증착된 막은 $800^{\circ}C$에서 20초간 급속 열처리 시 orthorhombic $TiSi_2$(C54 구조)로 결정화가 이루어졌다. 단결정 Si 기판과 다결정 Si에서 Ti-silicide 충으로의 dopant의내부 확산은 거의 발생하지 않았으며, 주입된 불순물들은 Ti-silicide/Si 계면 근처의 단결정 Si이나 다결정 Si 내부에 존재하고 있었다. 또한 형성된 Ti-silicide 박막의 표면 거칠기는 16-22nm이었다.

• 대한전자공학회논문지SD
• /
• 제39권5호
• /
• pp.1-7
• /
• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권3호
• /
• pp.252-258
• /
• 2013

In this paper, a thermally stable nickel silicide technology using the co-sputtering of nickel and titanium atoms capped with TiN layer is proposed for nano-scale metal oxide semiconductor field effect transistor (MOSFET) applications. The effects of the incorporation of titanium ingredient in the co-sputtered Ni layer are characterized as a function of Ti sputtering power. The difference between the one-step rapid thermal process (RTP) and two-step RTP for the silicidation process has also been studied. It is shown that a certain proportion of titanium incorporation with two-step RTP has the best thermal stability for this structure.

• 한국분말야금학회:학술대회논문집
• /
• 한국분말야금학회 2005년도 추계학술강연 및 발표대회강연 및 발표논문 초록집
• /
• pp.103-103
• /
• 2005

• 한국통신학회논문지
• /
• 제15권5호
• /
• pp.399-405
• /
• 1990

急速 熱處理 공정을 高融點 타이타늄 실리사이드 형성을 위한 反應率의 연구와 정확한 形成 調節에 이용하였다. 試料는 n형 실리콘과 다결정 웨이퍼이며, 타이타늄을 스퍼터로 증착시켰다. 工程은 질소와 아르곤 가스 분위기 下에 실리사이드 형성을 정확하게 조절하기 위해 急速 時間 溫度 분포의 行列로 수행하였다. 반응된 박막은 面抵抗 측정과 전자현미경 사진, 自動分 抛抵抗 측정, X-선 回折 등으로 分析하였다. 結果는 실리사이드의 抵抗度는 20$\mu$$\Omega$-cm이하 이고, 박막 두께는 타이타늄 燕着 의 두께보다 약 2배로 나타났다. 실리사이드 形成 분위기는 아르곤과 窒素가 同一한 溫度 時間 조건에서 形成되었다.

• 연구논문집
• /
• 통권29호
• /
• pp.163-171
• /
• 1999

A new titanium alloy system. Ti-xFe-ySi (x,y=0-4 wt%). was designed and characterized with the point at low cost and high strength for casting applications. Fe improved room and elevated temperature mechanical properties owing to solid solution hardening and beta phase stabilization. Si yielded titanium silicides and Si addition over 1 wt% resulted in poor ductility due to coarse silicide chains at prior beta boundaries. The optimum composition was found to be Ti-4Fe-(0.5-1)Si in the viewpoint of tensile strength and ductility which are comparable to the Ti-6Al-4V. The metal-mould reaction was also examined for Ti-xFe and Ti-xSi binary alloy system. The thickness of surface reaction layer w as not affected significantly with Fe content, while it was decreased with Si content. In the Ti-4Si alloy, no reaction layer was found. The depth of surface hardening layer was about $200\mum$ regardless of the mould materials.

• 한국전기전자재료학회논문지
• /
• 제13권9호
• /
• pp.729-734
• /
• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
• /
• pp.60-63
• /
• 2000

We have investigated the relationship between electrical and morphological properties of titanium silicide films. In this study, the C54 titanium silicides were formed by using high temperature sputtering and one-step annealing. From the measurement of electrical and morphological properties, a smooth surface and a relaxed roughness were observed for the titanium silicide film fabricated by high temperature sputtering. And it seems that the previous effect could improve electrical properties.

• 한국재료학회지
• /
• 제12권11호
• /
• pp.883-888
• /
• 2002

We investigated the void formation in composite-titanium silicide($TiSi_2$) process. We varied the process conditions of polycrystalline/amorphous silicon substrate, composite $TiSi_2$ deposition temperature, and silicidation annealing temperature. We report that the main reason for void formation is the mass transport flux discrepancy of amorphous silicon substrate and titanium in composite layer. Sheet resistance in composite $TiSi_2$ without patterns is mainly affected by silicidation rapid thermal annealing (RTA) temperature. In addition, sheet resistance does not depend on the void defect density. Sheet resistance with sub-0.5 $\mu\textrm{m}$ patterns increase abnormally above $850^{\circ}C$ due to agglomeration. Our results imply that $sub-750^{\circ}C$ annealing is appropriate for sub 0.5 $\mu\textrm{m}$ composite X$sub-750_2$ process.

• 한국분말재료학회지
• /
• 제12권6호
• /
• pp.447-452
• /
• 2005

The synthesis and consolidation of titanium silicide by electro-discharge-sintering has been investigated. As-received Ti powder was in flaky shape and the mean particle size was $45.0{\mu}m$, whereas the mean particle size of the pre-milled Si powder with angular shape was $8.0{\mu}m$. Single pulse of 2.5 to 5.0 kJ/0.34g-elemental Ti and pre-milled Si powder mixture with the composition of $Ti-37.5at.\%$ Si was applied using $300{\mu}F$ capacitor. The solid with $Ti_5Si_3$ phase has been successfully fabricated by the discharge with the input energy more than 2.5kJ in less than $129{\mu}sec.$ Hv values were found to be higher than $1000kgf/mm^2$. The formation of $Ti_5Si_3$ occurred through a fast solid state diffusion reaction.