• IEIE Transactions on Smart Processing and Computing
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• v.6 no.2
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• pp.133-139
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• 2017

Vehicles have increasingly evolved and become intelligent with convergence of information and communications technologies (ICT). Vehicle communications (VC) has become one of the major necessities for intelligent vehicles. However, VC suffers from serious security problems that hinder its commercialization. Hence, the IEEE 1609 Wireless Access Vehicular Environment (WAVE) protocol defines a security service for VC. This service includes Advanced Encryption Standard-Counter with CBC-MAC (AES-CCM) for data encryption in VC. A high-speed AES-CCM crypto module is necessary, because VC requires a fast communication rate between vehicles. In this study, we propose and implement an efficient AES-CCM hardware architecture for high-speed VC. First, we propose a 32-bit substitution table (S_Box) to reduce the AES module latency. Second, we employ key box register files to save key expansion results. Third, we save the input and processed data to internal register files for secure encryption and to secure data from external attacks. Finally, we design a parallel architecture for both cipher block chaining message authentication code (CBC-MAC) and the counter module in AES-CCM to improve performance. For implementation of the field programmable gate array (FPGA) hardware, we use a Xilinx Virtex-5 FPGA chip. The entire operation of the AES-CCM module is validated by timing simulations in Xilinx ISE at a speed of 166.2 MHz.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.108-114
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• 1995

Recently, along wtih the advance of high-performance system, synchronous DRAM's (SDRAM's) which provide consecutive data output synchronized with an external clock signal, have been reported. However, in the conventional SDRAM's which utilize a multi-stage serial pipelined scheme, the column path is divided into multi-stages depending on CAS latency N. Thus, as the operating speed and CAS latency increase, new stages must be added, thereby causing a large area penalty due to additinal latches and I/O lines. In the proposed register-based parallel pipelined scheme, (N-1) registers are located between the read data bus line pair and the data output buffer and the coming data are sequentially stored. Since the column data path is not divided and the read data is directly transmitted to the registers, the busrt read operation can easily be achieved at higher frequencies without a large area penalty and degradation of internal timing margin. Simulation results for 0.32um-Tech. 4-Bank 64M SDRAM show good operation at 200MHz and an area increment is less than 0.1% when CAS latency N is increased from 3 to 4.. This pipelined scheme is more advantageous as the operating frequency increases.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1702-1708
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• 2007

Dragon Stream Cipher is proposed for software base implementation in the eSTREAM project. Now this stream cipher is selected as a phase 3 focus candidate. Dragon is a new stream cipher contructed using a single word based NIFSR(non-linear feed back shift register) and 128/256 key/IV(Initialization Vector). Dragon is the keystream generator that produce 64bits of keystream. In this paper, we present an implementation of Drag(m stream cipher algorithm in hardware. Finally, the implementation is on Altera FPGA device, EP3C35F672I and the timing simulation is done on Altera's Quartus II. A result of 111MHz maximum clock rate and 7.1Gbps is throughput is obtained from the implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1201-1210
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• 1990

This paper proposes on-chip instruction and data cache memories on RISC reduced instruction set computer) architecture which supports fast instruction fetch and data read/write, and enables RISC processor under research to obtain high performance. In the execution of HLL(high level language) programs, heavily used local scalar variables are stored in large register file, but arrays, structures, and global scalar variables are difficult for compiler to allocate registers. These problems can be solved by on-chip Instruction/Data cache. And each cycle of instruction fetch, pad delay causes the lowering of the processors's performance. Cache memories are designed in CMOS technology and SRAM(static-RAM), that saves layout area and power dissipation, is used for instruction and data storage. To speed up and support RISC processor's piplined architecture efficiently, hardwired logic technology is used overall circuits i cache blocks. The schematic capture and timing simulation of proposed cache memorises are performed on Apollo DN4000 workstation using Mentor Graphics CAD tools.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.9-19
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• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1393-1399
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• 1999

In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.4
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• pp.18-26
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• 2001

In this paper, we propose an ATC(Automatic Transfer mode Controller) algorithm and an average-mode-change method for use in Gear shift PLL which can automatically change loop gain. The proposed ATC algorithm accurately detects proper timing or the mode change and has a very simpler structure - than the conventional lock detector algorithm often used in QPSK. And the proposed average mode change method can obtain low errors of estimated frequency offset by averaging the loop filter output of frequency component in shift register. These algorithms are also useful in designing ASIC, since these algorithms occupy small circuit area and are adaptable for high speed digital processing. We also present phase tracking performance of proposed Gear-shift PLL, which is composed of polarity decision PD, ATC and average mode change circuit, and analyze the results by examining constellation at each mode.

• Journal of the Korea Society of Computer and Information
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• v.23 no.1
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• pp.33-39
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• 2018

In this paper, We studied the possibility of SoC(System On Chip) design using infrared image processing IP(Intellectual Property). And, we studied NUC(Non Uniformity Correction), BPR(Bad Pixel Recovery), and CEM(Contrast Enhancement) processing, the infrared image processing algorithm implemented by IP. We showed the logic and timing diagram implemented through the hardware block designed based on each algorithm. Each algorithm was coded as RTL(Register Transfer Level) using Verilog HDL(Hardware Description Language), ALTERA QUARTUS synthesis, and programed in FPGA(Field Programmable Gated Array). In addition, we have verified that the image data is processed at each algorithm without any problems by integrating the infrared image processing algorithm. Particularly, using the directly manufactured electronic board, Processor, SRAM, and FLASH are interconnected and tested and the verification result is presented so that the SoC type can be realized later. The infrared image processing IP proposed and verified in this study is expected to be of high value in the future SoC semiconductor fabrication. In addition, we have laid the basis for future application in the camera SoC industry.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1210-1217
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• 2004

LILI-II stream cipher is an upgraded version of the LILI-128, one of candidates in NESSIE. Since the algorithm is a clock-controlled, the speed of the keystream data is degraded structurally in a clock-synchronized hardware logic design. Accordingly, this paper proposes a 4-bit parallel LFSR, where each register bit includes four variable data routines for feedback or shifting within the LFSR. furthermore, the timing of the proposed design is simulated using a Max+plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and apply to the Lucent ASIC device (LV160C, 0.13${\mu}{\textrm}{m}$ CMOS ＆ 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13${\mu}{\textrm}{m}$ semiconductor for the maximum path delay below 1.8㎱. Finally, we propose the m-parallel implementation of LILI-II, throughput with 4, 8 or 16 Gbps (m=8, 16 or 32).