• International Journal of Aeronautical and Space Sciences
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• v.18 no.3
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• pp.389-394
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• 2017

The limitation of flow control for a bistable fluidic valve has been investigated. The physical model of the fluidic valve includes two main flow outlets and two control flow inlets. The experiments were conducted with pressure regulators, mass flow meters, and piezo sensors to analyze flow switching characteristics of the fluidic valve. The experimental data such as pressure and mass flow rate of control flows and the switching time of the main flow was obtained with various operating conditions. The operation limit of the fluidic valve is identified, and a model equation for pre-estimating the minimum control pressure to switch the direction of the main flow has been proposed.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.160-162
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• 2020

A control technique for the auxiliary buck/boost converter is proposed herein to improve the load transient response of the buck converter. The proposed technique improves the system efficiency by enabling the soft switching operation of the auxiliary converter. The design guidelines for achieving capacitor charge balance for the output capacitor during the transient are also presented herein. The experimental results revealed that the output voltage undershoot and settling time during the load step-up transient were 40 mV and 14 ㎲, respectively, and the output voltage overshoot and settling time during the load step-down transient were 35 mV and 21 ㎲, respectively. The performance and effectiveness of the proposed technique were experimentally verified using a prototype buck converter with a 15-V input, 3.3-V output, and 200-kHz switching frequency.

• The Korean Journal of Applied Statistics
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• v.27 no.6
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• pp.1049-1068
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• 2014

Autoregressive models are used to analyze an univariate time series data; however, these methods can be inappropriate when a structural break appears in a time series since they assume that a trend is consistent. Threshold autoregressive models (popular regime-switching models) have been proposed to address this problem. Recently, the models have been extended to two regime-switching models with delay parameter. We discuss two regime-switching threshold autoregressive models from a Bayesian point of view. For a Bayesian analysis, we consider a parametric threshold autoregressive model and a nonparametric threshold autoregressive model using Dirichlet process prior. The posterior distributions are derived and the posterior inferences is performed via Markov chain Monte Carlo method and based on two Bayesian threshold autoregressive models. We present a simulation study to compare the performance of the models. We also apply models to gross domestic product data of U.S.A and South Korea.

• Journal of Power Electronics
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• v.16 no.1
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• pp.227-237
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• 2016

A novel digital current control strategy for digitally controlled DC-DC switching converters, referred to as Adjacent Cycle Sampling (ACS), is proposed in this paper. For the ACS current control strategy, the available time interval from sampling the current to updating the duty ratio, is approximately one switching cycle. In addition, it is independent of the duty ratio. As a result, the contradiction between the processing speed of the hardware and the transient response speed can be effectively relaxed by using the ACS current control strategy. For digitally controlled buck DC-DC switching converters with trailing-edge modulation, digital current control algorithms with the ACS control strategy are derived for three different control objectives. These objectives are the valley, average, and peak inductor currents. In addition, the sub-harmonic oscillations of the above current control algorithms are analyzed and eliminated by using the digital slope compensation (DSC) method. Experimental results based on a FPGA are given, which verify the theoretical analysis results very well. It can be concluded that the ACS control has a faster transient response speed than the time delay control, and that its requirements for hardware processing speed can be reduced when compared with the deadbeat control. Therefore, it promises to be one of the key technologies for high-frequency DC-DC switching converters.

• Journal of Electrochemical Science and Technology
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• v.15 no.3
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• pp.405-413
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• 2024

Several techniques for determining the reverse peak current from a cyclic voltammogram (CV) for a reversible system are described in the literature: CV itself as a baseline with long switching potential (E_λ) that serves as a baseline for other CVs, Nicholson equation that uses CV parameters to calculation reverse peak current and linear extrapolation of the current obtained at the switching potential. All methods either present experimental difficulties or large errors in the peak current determination. The paper demonstrates, both theoretically and experimentally, that trapezoidal cyclic voltammetry (TCV) can be used as a baseline to determine anodic peak current (i_ap) with high accuracy and with a switching potential shorter than that used by CV, as long as E_λ is at least 130 mV away from the cathodic peak. Beyond this value of switching potential the electroactive specie is completely depleted from the electrode surface. Using TCV with E_λ = 0.34 V and a switching time (t_λ) of 240 s as a baseline, the determination of the reverse peak current presents a deviation from the expected value of less than 1% for most of the CVs studied (except cases when E_λ is close to the direct potential peak). This result presents better accuracy than the Nicholson equation and the linear extrapolation of the current measured at the switching potential, in addition to presenting a smaller error than that obtained in the acquisition of the experimental current. Furthermore, determining the reverse peak current by extrapolating the linear fit of i_ap vs. ${\sqrt[1/]{t_{\lambda}}}$ to infinite time gave a reasonable approximation to the expected value. Experiments with aqueous potassium hexacyanoferrate (II) and ferrocene in acetonitrile confirmed the theoretical predictions.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.6
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• pp.610-617
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• 2011

This paper proposes a novel and direct dead-time compensation method of the 3-phase inverter using space vector pulse width modulation(SVPWM) topology. The proposed dead-time compensation method directly compensates the dead-time to the turn-on time of the effective voltage vector according to the current direction of the medium voltage reference. Each phase voltages are determined by the switching times of the effective voltage vectors, and the practical switching times have loss according to the current direction by the dead-time effect in the 3-phase inverter. The proposed method adds the dead-time to the switching time of the effective voltage vector according to the current direction, so it does not require complex d-q transform and controller to compensate the voltage error. The proposed dead-time compensation scheme is verified by the computer simulation and experiments of 3-phase R-L load.

• The KIPS Transactions:PartC
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• v.11C no.4
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• pp.527-538
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• 2004

In this paper, we present the flow aggregation method and the FLTC(flow lasting time control) algorithm to reduce the number of flows and solve the scalability problem in high speed IP switching networks. The flow aggregation based on the destination address could reduce the total number of flows, improve the label efficiency, and increase the total amount of the switched packets. The FLTC algorithm also eliminates the waste of label by deleting the flow binding efficiently. With the traces of real Internet traffics, we evaluate the performance of these schemes by simulation. The label efficiency, the average number of label used, and the percentage of packets switched and the number of packets switched are used as performance measures for this simulation.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1015-1019
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• 2001

This paper presents a novel three-phase current-fed Pulse Width Modulation converter with switched capacitor type resonant DC link commutation circuit operating PWM pattern strategy under a design consideration of low-pass filter, which can operate on the basis of the principle of zero current soft switching commutation. In the first place, the steady state operating principle of this converter with a new resonant DC link snubber circuit is described in connection with the equivalent operation circuit, together with the practical design procedure of the switched-capacitor type resonant DC link circuit is discussed from a theoretical viewpoint on the basis of a design example for high-power applications. The actively delayed time correction method to compensate distorted currents due to a relatively long resonant commutation time is newly implemented in the open loop control scheme so as to acquire the new optimum PWM pattern. Finally, the experiment of set-up in laboratory system of this converter is concretely demonstrated herein to confirm a zero current soft-switching commutation of this converter. The comparative evaluations between current-fed hard switching PWM and soft-switching PWM converters are carried out from a viewpoint of their PWM converter characteristics.

• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.4
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• pp.225-233
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• 2010

In this paper, we try to improve the performance of the demand paging loader suggested to use the demand paging way that is not based on operating system. The demand paging switching strategy used in the existing operating system can know the recently used pages by running multi-processing. Then, based on it, some page switching strategies have been made for the recently used pages or the frequently demanded pages. However, the strategies based on operating system cannot be applied in single processing that is not based on operating system because any context switching never occur on the single processing. So, this paper is trying to suggest the demand paging switching strategies that can be applied in paging loader running in single process. In the Return-Prediction-Algorithm, we saw the improved performance in the program that the function call occurred frequently in a long distance. And then, in the Most-Frequently-Used-Page-Remain-Algorithm, we saw the improved performance in the program that the references frequently occurred for the particular pages. Likewise, it had an enormous effect on keeping the memory reduction performance by the demand paging and reducing the running time delay at the same time.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.8
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• pp.463-467
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• 2000

In this paper, the new LIGBT structures with trap injection are proposed to improve switching characteristics of the conventional SOI LIGBT. The Simulations are performed in order to investigate the effects of the positiion, whidth and concentration of trap injection region with a reduced minority carrier lifetime using 2D device simulator MEDICI. Their electrical characteristics are analyzed and the optimum design parameters are extracted. As a result of simulation, the turn off time for the model A with the trap injection is $0.78\mus$. These results indicate the improvement of about 2 times compared with the conventional SOI LIGBT because trap injection prevents minority carriers which is stored in the n-drift region during turn off switching. The latching current is $1.5\times10^{-4}A/\mum$ and forward blocking voltage is 168V which are superior to those of conventional structure. It is shown that the trap injection is very effective to reduce the turn off time with a little increasing of on-state voltage drop if its design and process parameters are optimized.