• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.101-105
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• 2024

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the D_it.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.6
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• pp.1081-1086
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• 2023

The rapid growth and increasing complexity of modern networks have highlighted the limitations of traditional network architectures. The emergence of SDN (Software-Defined Network) in response to these challenges has changed the existing network environment. The SDN separates the control unit and the data unit, and adjusts the network operation using a centralized controller. However, this structure has also recently caused a huge amount of traffic due to the rapid spread of numerous Internet of Things (IoT) devices, which has not only slowed the transmission speed of the network but also made it difficult to ensure quality of service (QoS). Therefore, this paper proposes a method of load distribution by switching the IP and any server (processor) from the existing data processing scheduling technique, RR (Round-Robin), to mapping when a large amount of data flows in from a specific IP, that is, server overload and data loss.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.3
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• pp.166-175
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• 2024

In this paper, the Window-Masking Method and HAT (Hardware Attached Top) CPU SoM (System on Module) are used to improve the performance and reduce the weight of the MANET (Mobile Ad-hoc Network) network synchronization system using time division redundancy. We propose converting it into a RISC-V based soft-core MCU and mounting it on an FPGA, a hardware accelerator. It was also verified through experiment. In terms of performance, by applying the proposed technique, the synchronization acquisition range is from -50dBm to +10dBm to -60dBm to +10dBm, the lowest input level for synchronization is increased by 20% from -50dBm to -60dBm, and the detection delay (Latency) is 220ns. Reduced by 43% to 125ns. In terms of weight reduction, computing resources (48%), size (33%), and weight (27%) were reduced by an average of 36% by replacing with soft-core MCU.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.367-376
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• 2007

In this paper, we introduce an application-specific and adaptive power management technique for portable systems that support dynamic voltage scaling (DVS). We exploit both the idle time of multitasking systems running soft real-time tasks as well as memory- or CPU-bound code regions. Detailed power and execution time profiles guide an adaptive power manager (APM) that is linked to the operating system. A post-pass optimizer marks candidate regions for DVS by inserting calls to the APM. At runtime, the APM monitors the CPU's performance counters to dynamically determine the affinity of the each marked region. for each region, the APM computes the optimal voltage and frequency setting in terms of energy consumption and switches the CPU to that setting during the execution of the region. Idle time is exploited by monitoring system idle time and switching to the energy-wise most economical setting without prolonging execution. We show that our method is most effective for periodic workloads such as video or audio decoding. We have implemented our method in a multitasking operating system (Microsoft Windows CE) running on an Intel XScale-processor. We achieved up to 9% of total system power savings over the standard power management policy that puts the CPU in a low Power mode during idle periods.

• The KIPS Transactions:PartB
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• v.12B no.6 s.102
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• pp.679-684
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• 2005

There are a few representative wireless network access technologies used widely. WWAN is celluar based telecommunication networks supporting high mobility, WLAN ensures high data rate within hotspot coverage, and WDMB support both data and broadcasting services correspondingly. However, these technologies include some limitations especially on the mobility, data rate, transmission direction, and so on. In order to overvome these limitations, there are various studies have been proposed in terms of 'Vortical Handoff' that offers seamless connectivity by switching active connection to the appropriate interface which installed in the mobile devices. In this paper, we propose the interface selection algorithm and network architecture to maximize the life time of entire system by minimizing the unnecessary energy consumption of another interfaces such as WLAN, WDMB that are taken in the user equipment. In addition, by using the results of analyzing multiple types of traffic and managing user buffer as a metric for vertical handoff, we show that the energy efficiency of our scheme is $75\%$ and $34\%$ than typical WLAN for WDMB and WLAN preferred schemes, correspondingly.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• Cartoon and Animation Studies
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• s.14
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• pp.151-164
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• 2008

Cross platform game has brought about the expansion of game market, which results in technology innovation overcoming the limit of game consumption. The new model integrates both off and online game services. Gamers can now enjoy game service regardless of age, time, and space. If the technology evolution model of digital contents like cross-platform game engine can provide contents for several platform at the same time, the interactive service can be utilized into maximum level. It is also necessary to allocate, switch data as well as to innovate the transmission technology of data according to each platform. Providing the same contents for several platform as many as possible can be the most suitable strategy to enhance the efficiency and profits. However if the interactive service can be accomplished completely, the development of data switching technology and distribution should be made. To be a leader in the next digital contents market, one should develop the network engine technology which can embody the optimization of consumption in the interactive network service.

• Korean Journal of Veterinary Research
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• v.35 no.4
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• pp.815-822
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• 1995

The toxicokinetics of rifapentine was studied after an oral administration to beagle dogs. High-performance liquid chromatography(HPLC) using column-switching technique was performed to determine the serum concentrations of rifapentine. The pharmacokinetic profiles of rifapentine were analysed using one-compartment open model. Following a single oral administration of 10mg/kg, pharmacokinetic parameters were determined as follows: maximum serum concentration($C_{max}$), $28.90{\mu}g/ml$; maximum concentration time($T_{max}$), 3.7hr; elimination half-life($t_{1/2}$, 4.7hr; area under the curve(AUC), $339.0{\mu}g{\cdot}hr/ml$; volume of disiribution/bioavailability (Vd/F), 0.21 l/kg; lag time, 24min; absorption rate constant($k_a$), $0.445hr^{-1}$; elimination rate constant($k_{el}$), $0.148hr^{-1}$. After 6 month multiple oral doses of 10mg/kg/day, parameters were as follows: $C_{max}$, $34.40{\mu}g/ml$; $T_{max}$, 2.6hr; $t_{1/2}$, 6.7hr; AUC, $391.3{\mu}g{\cdot}hr/ml$; Vd/F, 0.291/kg; $k_a$, $0.976hr^{-1}$; $k_{el}$, $0.104hr^{-1}$. The consistant kinetic parameters after a single and multiple oral administration show that there was no accumulation of rifapentine after 6 month oral administration. We also simulated the concentration of rifapentine after oral multiple administration of 10 and 50mg/kg/ day, based on the parameters obtained form the single administration. The measured serum concentrations of rifapentine were well fitted to the simulated results. The simulated results show that rifapentine readily reaches to steady-state after about 3 doses and the steady-state serum concentrations($C_{ss}$) are fluctuated in between $2.2{\sim}25.2{\mu}g/ml$, and $10.6{\sim}125.2{\mu}g/ml$ at the doses of 10 and 50mg/kg/day, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.1
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• pp.32-39
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• 2015

The voice communications with wireless backbone based networks are evolving into a packet switching VoIP systems. In those networks, a call processing scheme is required for management of subscribers and connection between them. A VoIP service scheme for those systems requires reliable subscriber management and connection establishment schemes, but the conventional call processing schemes based on the centralized server has lack of reliability. Thus, the mutual-backup architecture of SIP-servers is required to ensure efficient subscriber management and reliable VoIP call processing capability, and the synchronization and call processing schemes should be changed as the architecture is changed. In this paper, a mutual-backup architecture of SIP-servers is proposed for wireless backbone based networks. A message format for synchronization and information exchange between SIP servers is also proposed in the paper. This paper also proposes a FSM scheme for the fast call processing in unreliable networks to detect multiple servers at a time. The performance analysis results show that the mutual backup server architecture increases the call processing success rates than conventional centralized server architecture. Also, the FSM scheme provides the smaller call processing times than conventional SIP, and the time is not increased although the number of SIP servers in the networks is increased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.