• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.567-574
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• 2015

In this paper, a 50ns 256-kb EEPROM IP for MCU (micro controller unit) ICs is designed. The speed of data sensing is increased in the read mode by using a proposed DB sensing circuit of differential amplifier type which uses the reference voltage, and the switching speed is also increased by reducing the total DB parasitic capacitance as a distributed DB structure is separated into eight. Also, the access time is reduced reducing a precharging time of BL in the read mode removing a 5V NMOS transistor in the conventional RD switch, and the reliability of output data can be secured by obtaining the differential voltage (${\Delta}V$) between the DB and the reference voltages as 0.2*VDD. The access time of the designed 256-kb EEPROM IP is 45.8ns and the layout size is $1571.625{\mu}m{\times}798.540{\mu}m$ based on MagnaChip's $0.18{\mu}m$ EEPROM process.

• Journal of Power Electronics
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• v.18 no.2
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• pp.558-572
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• 2018

In addition to its modular nature, a Hybrid Modular Multilevel Converter (HMMC) assembled from half-bridge and full-bridge sub-modules, is able to block DC faults with a minimum number of switching devices, which makes it attractive for high power applications. This paper introduces a control strategy based on the Root-Least Square (RLS) algorithm to estimate the capacitor voltages instead of using direct measurements. This action eliminates the need for voltage transducers in the HMMC sub-modules and the associated communication link with the central controller. In addition to capacitor voltage balancing and suppression of circulating currents, a fault tolerant control unit (FTCU) is integrated into the proposed strategy to modify the parameters of the HMMC controller. On advantage of the proposed FTCU is that it does not need extra components. Furthermore, a fault detection unit is adapted by utilizing a hybrid estimation scheme to detect sub-module faults. The behavior of the suggested technique is assessed using PSCAD offline simulations. In addition, it is validated using a real-time digital simulator connected to a real time controller under various normal and fault conditions. The proposed strategy shows robust performance in terms of accuracy and time response since it succeeds in stabilizing the HMMC under faults.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.169-177
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• 2012

A non-decimation second-order spatial moving average (SMA) discrete-time (DT) filter is proposed with reconfigurable null frequencies. The filter coefficients are changeable, and it can be controlled by switching sampling capacitors. So, interferers can be rejected effectively by flexible nulls. Since it operates without decimation, it does not change the sample rate and aliasing problem can be avoided. The filter is designed with variable weight of coefficients as $1:{\alpha}:1$ where ${\alpha}$ varies from 1 to 2. This corresponds to the change of null frequencies within the range of fs/3~fs/2 and fs/2~2fs/3. The proposed filter is implemented in the TSMC 0.18-${\mu}m$ CMOS process. Simulation shows that null frequencies are changeable in the range of 0.38~0.49fs and 0.51~0.62fs.

• Journal of Advanced Navigation Technology
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• v.21 no.3
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• pp.220-229
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• 2017

In this paper, To take advantage a variety of DC power as the boost DC-DC converter design specifications through the inductor L and capacitor C through PSPICE to calculate the best estimate of the value. Boost DC-DC converter with a switch device using IRF840 and reverse recovery time Schottky diodes with excellent with constant current controller using D10SC6M and resistance can be configured to considering the Power LED Module was driven by the production. Converter's switching frequency is 50 kHz, the first Duty Rate was made to increase gradually depending on the value of the detection were, 10 % in the output voltage. As a result, the simulated Boost Power LED driver characteristics is in comparison with the design specifications, 5% or less as the error was approximated. Finally, when input 15 V were offered, a stable output 24 V were obtained. and Dimming Control through the adjustment of brightness and current consumption were possible.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.1
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• pp.153-162
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• 2018

The importance of energy harvesting technique is increasing due to the elevated level of demand for sustainable power sources for wearable device applications. In this study, we developed an Energy Harvesting wearable Platform(EH-P) architecture which is used in the design of a multi-energy source based on TENG. The proposed switching circuit produces power with higher current at lower voltage from energy harvesting sources with lower current at higher voltage. This can powers microcontrollers for a short period of time by using PV and TENG complementarily placed under hard conditions for the sources such as indoors. As a result, the whole interface circuit is completely self-powered with this makes it possible to run of sensing on a Wearable device platform. It was possible to increase the wearable device life time by supplying more than 29% of the power consumption to wearable devices. The results presented in this paper show the potential of multi-energy harvesting platform for use in wearable harvesting applications, provide a means of choosing the energy harvesting source.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.10
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• pp.52-63
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• 1998

In this paper, several improvements to a copy network proposed previously for multicast packet switching are described. The improvements provide a solution to some problems inherent in multicasting. The input fairness problem caused by overf low is solved by a dynamic starting point decider(DSD), which can calculate running sums of copy requests starting from any input port. The starting point is changed adaptively in every time slot based on both the fill level of the input buffers in current time slot and the overflow situations of the previous time slot. Using the fill level of the conventional network. The DSD also provides the function of regulating overall copy requests according to the amount of input traffics. This is an essential function in improving overall throughputs of the copy networks. The throughput of a multicast switch can be improved substantially if partial service of copy request is implemented when overflow occurs. Call-splitting can also be implemented by the DSD in a straightforward manner. The hardware for the DSD is derived with the objective of simple architectures for the high speed operation. Simulation study of the copy network under various traffic conditions is presented to evaluate its performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.12
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• pp.61-68
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• 2010

In this paper, we investigate the performance of ARQ-aided Time Switched Transmit Diversity (ARQ-TSTD) applying the multi-level control signaling in the WCDMA LCR-TDD system. Proposed ARQ-TSTD system applies the multi-level control signaling scheme in which the receiver sends the response signal (ACK or NACK signal) to the transmitter and defines NACK2 signal for multi-level control. Transmitter utilize the NACK2 control signal to the postponement of transmission and multi-user scheduling scheme proposed by this paper. Simulation results demonstrate that the proposed postponement of transmission and multi-user scheduling scheme yield about 1.3dB, 1.4dB performance gain respectively, compared with the conventional ARQ-TSTD with antenna switching scheme in tenn of the frame error rate (FER) for mobile speed of 3km/h and FER value of 10%. In addition, 14% and 11.5% of throughput gain respectively is shown when Eb/N0=-3dB.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.12
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• pp.61-67
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• 2015

Certainly, we are living in a true mobile society. At the end of 2014, approximately 40million 560thousand people are subscribed to smartphone services in Korea, using more than 2000MB of mobile data per a person. The use of smartphone is expected to increase. Moreover, smartphone moves toward becoming a requisite for modern people. Under the circumstances, high-speed communication services such as LTE provide high quality services anywhere and anytime and, furthermore, the development of high performances of the application makes the life patterns of modern people link directly to smartphone. Almost every day, new creative services are being introduced and the demands of on-line streaming services such as high-performance game and YouTube are increasing day after day. However, although smartphones are getting smarter and high quality services are rapidly growing, consumers still complain about the insufficient usage time caused by the capacity of batteries. In order to solve this problem, this thesis suggests EDLC(Electric Double-Layer Capacitor) uses as a supplemental power supply to keep the continuity of work while switching batteries. Through this approach, the running time of smartphone becomes longer as the number of batteries without power off and the purpose of this study is to maximize the convenience of using smartphone by eliminating the initialization of memories and the loss of time of rebooting while batteries are switched.