• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.720-725
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• 1991

In this thesis, the lead-lag compensator is designed to improve output characteristics of flyback zero voltage switching quasi-resonant converters. The switch and the diode are assumed ideally. And the SMPS is modelled by state equations with four operation modes. And the model for controller design is also achived by using a state space averaging method, which is continuous time average of state variables every period. The lag, the lead and the lead-lag compensator is designed the SMPS respectively. The time domain analysis and the frequency domain analysis are done for each compensated circuit. It is possible increasing the phase margin and improving the transient response by the compensators. The phase lag compensator has small overshoot comparatively. But the bandwidth is narrower than the others, so it has longest settling time. For the phase lead compensator, the response come to steady-state within short period. But the overshoot is the largest due to its large peak gain. Finally, the phase lead-lag compensator has medium characteristics in the overshoot and the settling time.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.111-117
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• 1998

This paper presents a polarity changing method without dead time of a cycloconverter with an LC resonant circuit. According to the proposed method, dead time to prevent short circuit for the polarity changing is not required. Therefore the delay of control and the harmonic components of output currents can be decreased. And the proposed method can be expanded for the other natural commutated cycloconverters of noncirculating current type. In this paper, the switching method of the proposed polarity changing without dead time is studied, and in order to confirm the validity of the proposed method the experiment is carried out with a cycloconverter with an LC resonant circuit.

• Proceedings of the KIEE Conference
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• 2002.07a
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• pp.70-73
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• 2002

Utilities are trying to install the equipment of high quality to avoid deterioration of supply reliability. In addition, many sectionalizing switches which can decrease the total outage value for a fault are installed for the same reason. Therefore, utilities are interested in standards and criteria for installing switches to optimize the total cost on distribution systems. The affect of sectionalizing switches installed on distribution feeder is gradually decreased because the failure rate on distribution feeder is decreased. Also the automation for distribution systems is widely applied for the efficient operation. Therefore, the renewal for installation standards of sectionalizing switches is required to reflect the current operation situation. The variable data is used to consider the KEPCO's real situation of distribution feeder as follows; the feeder capacity, connecting rate, feeder length, failure rate of distribution feeder, the failure rate of switches, perception time of feeder fault, the restoration time for a faulted section, the transfer time to other feeders, and the switching time. In this study, We propose equations which can determine the number of sectionalizing switches for minimizing the outage and switch installation cost.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.2
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• pp.26-37
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• 2003

An optimal software release, which is related to the development cost, error detection and correction under the various operation systems, is a critical factor for managing project. This paper described optimal software release issues to predict the release time of large switching system with the system stability point of view and evaluated a timely supply of target system, proper utilization of resources under the software reliability valuation basis. Finally, Using initial failure data, based on the exponential reliability growth model methodology, optimal release time, and analysis of failure data during the system testing and managing methodologies were presented.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.2B no.3
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• pp.81-89
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• 2002

The sensorless AC motor drive is a popular topic of study due to the cost and reliability of speed and position sensors. Most sensorless algorithms are based on the mathematical modeling of motors including electrical variables such as phase current and voltage. Therefore, the accuracy of such variables largely affects the performance of the sensorless AC motor drive. However, the output voltage of the SVPWM-VSI, which is widely used in sensorless AC motor drives, has considerable errors. In particular, the SVPWM-VSI is error-prone in the low speed range because the constant DC link voltage causes poor resolution in a low output voltage command and the output voltage is distorted due to dead time and voltage drop. This paper investigates a novel high-performance strategy for overcoming these problems in a sensorless ac motor drive. In this paper, a variation of the DC link voltage and a direct compensation for dead time and voltage drop are proposed. The variable DC link voltage leads to an improved resolution of the inverter output voltage, especially in the motor's low speed range. The direct compensation for dead time and voltage drop directly calculates the duration of the switching voltage vector without the modification of the reference voltage and needs no additional circuits. In addition, the proposed strategy reduces a current ripple, which deteriorates the accuracy of a monitored current and causes torque ripple and additional loss. Simulation and experimentation have been performed to verify the proposed strategy.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.8-10
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• 2005

In a general purpose inverter, a dead-time compensation strategy is very important for reducing torque ripples and acoustic noises of motors. However, in the case of small capacity inverter, the accurate dead-time compensation is hard to be obtained because a removal of the switching noise in a feedback current signal is difficult on condition of low-cost implementation. In this paper, the operation characteristics of the general purpose inverter applied the dead time compensation algorithm using an instantaneous back calculation of the phase angle of the current are presented.

• The Transactions of the Korea Information Processing Society
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• v.6 no.10
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• pp.2764-2771
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• 1999

ATM has recently received much attention because of its high capacity, its bandwidth scalability, and its ability to support multiservice traffic. However, ATM is connection oriented whereas the vast majority of modern data networking protocols are connectionless. The alternative to support current service on ATM will be a router with attached switching hardware that has the ability to cache routing decisions. In this paper, we described the router using a switch and simulated the performance. From the results of the simulation, the routing delay was decreased as the number of flow channels. Cell-delay was shortest at 30,000 cell-time when the keeping time of a flow channel was. The line utilization was rapidly decrease when a flow-setup time is 20 30 cell-time. The results of this simulation could be applied to predict the performance of the router using ATM switch.

• The Transactions of the Korea Information Processing Society
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• v.6 no.7
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• pp.1941-1954
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• 1999

This paper presents a design and implementation of CRs(CHILL Run-time support System) to adapt the concurrent processing facilities of CHILL(CCITT High Level Language) which had recommended by ITU-T(International Telecommunication Union Telecommunication Standardization Sector). Because the CHILL provides more various concurrent processing facilities that other concurrent programming language, a design and implementation on CRS can give us real effects to gain the major functionalities and the techniques of the concurrent processing. In this paper, we design the interface rules of concurrent functions to conform with the CHILL compiler. We use the concurrent processing primitives as the library style to be invoked by procedure calls, and implement the start-up routine of the CHILL program, the context switching routine, and the CHILL process control parts to control be execution of the CHILL processes concurrently.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.9
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• pp.34-40
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• 1999

In order to establish the design technique of the robust current controller in d.c series wound motor driver system, this paper proposes a method of the compensated Bang-Bang current control using d.c series wound motor driver system under the improperly variable load to get minimum time for the torque control. The compensated Bang-Bang current controller structure is simpler than that of PID plus Bang-Bang controller. This paper shows that a general 16 bits microprocessor is efficiently used to implement such an algorithm. The calculation time of software is extremely small when compared with that of conventional PID plus Bang-Bang controller. Both nonlinear operating characteristics of digital switching elements and describing function methods are used for the analysis and synthesis. Real-time implementation of the compensated Bang-Bang current controller is achieved. The concept of design strategy of the control and the PWM waveform generation algorithms are presented in this paper.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.1 no.1
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• pp.42-49
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• 1983

전산기의 신뢰도(reliability)라 함은 사용자가 제출한 입력에 대하여 전산 기가 제공하는 결과의 신빙성의 척도라할 수 있는데, 이것은 주어진 전산기의 부 분품 하나하나가, 그리고 프로그램의 하나하나의 instruction이 설계당시에 목적한 성능을 얼마나 잘 유지하고 있는가를 측정하는 척도라고 볼 수 있습니다. 이 신 뢰도는 전산기의 수명, 필요할 때 전산기가 가동할 확율, 또는 전산기의 성능으로 나타낼 수 있습니다. 제2세대 이전의 전산기들에서는 전자공업과 전산기 기술의 불충분한 발전으로 인하여 비용과 기계의 크기의 한정 때문에 신뢰도 향상을 위 한 대책이 거의 없었습니다. 따라서 현재 볼 수 있는 American Air Line의 SABRE(Semi Automatic Business Research Environment), Bell 전화 연구소의 ESS-I, II, III(Electronic Switching System), IBM의 FMS(Future Manufacturing System)과 같은 real-time 씨스템으로서의 응용분야의 개발은 상 당히 어려운 문제였습니다. 그러나 전자공업의 비약적인 발전에 힘입어 금세대의 범용전산기의 설계가 가능하게 되었고, 오퍼레이팅 씨스템의 발전으로 인하여 multiprogramming, time-sharing, real-time 씨스템 등의 응용분야의 개발이 활발 하게 되었습니다. 이러한 응용분야의 활발한 개발과, 대규모 집적회로 (LSI)의 개 발로 ROM(Read Only Memory)의 가격화, 그리고 microprogram의 보급 등으로 특수 목적의 time sharing operation을 위한 소형 전산기가 발전하게 되었으며 종 래의 범용 전산기 대신에 CDC의 string unit과 pipeline을 이용한 STAR 100과 일리노이 대학의 256processor와 Burrough의 B6500로 구성된 ILLIAC-IV와 같은 초대형 전산기가 등장하게 되었습니다.