• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.11
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• pp.859-865
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• 1991

The paper proposes a design of high-speed dynamic CMOS PLA (Programmable Logic Array) which performs stable circuit operation. The race problem which nay occur in a NOR-NOR implementation of PLA is free in the proposed dynamic CMOS PLA by delaying time between the clocks to the AND- and to the OR-planes. The delay element has the same structure as the product line of the longest delay in the AND p`ane. Therefore it is unnecessary to design the delay element or to calculate correct delay time. The correct delay generated by the delay element makes the dynamic CMOS PLA to perform correct and stable circuit operation. Theproposed dynamic CMOS PLA has few variation of switching delay with the increasing number of inputs or outputs in PLA. It is verified by SPICE circuit simulation that the proposed dynamic CMOS PLA has the better performance over existing dynamic CMOS PLA's.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.2
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• pp.110-114
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• 2014

In this study, we report the doping effect of graphene quantum dots (QDs) in nematic liquid crystal (NLC) system on rubbed polyimide (PI) surface. The good LC alignment and high thermal stability in QD-LC cell system on rubbed PI surfaces can be measured. Also, the low threshold voltage of QD-TN cell was observed about 2.77 V. The fast response time of 13.2 ms for QD-TN cell can be achieved. Finally, the good voltage holding ratio of QD-TN cell on rubbed PI surface was measured.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.4
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• pp.345-350
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• 2014

DC electrolytic capacitor is widely used in the power converter including PWM inverter, switching power supply and PFC Boost converter system because of its large capacitance, small size and low cost. In this paper, basic characteristics of DC electrolytic capacitor vs. frequency is presented and the real-time estimation scheme of ESR and capacitance based on the bandpass filtering is adopted to the single phase boost converter of uninterruptible power supply to diagnose its split dc-link capacitors. The feasibility of this real-time failure prediction monitoring system is verified by the computer simulation of the 5[kW] singe phase PFC half-bridge boost converter.

• Proceedings of the KIPE Conference
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• 2019.11a
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• pp.180-181
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• 2019

This paper proposes a method for improving the power quality of PMSG-based wind energy conversion system based on model predictive control in DC Microgrid. The MPC has a fast dynamic response. However, a large torque ripple deteriorating power quality is generated by a large and fixed switching period. On the other hand, the proposed method improves the power quality by setting the sampling time having zero torque error. The validity of the proposed method is verified through PSIM simulation.

• Journal of the Korea Society for Simulation
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• v.11 no.2
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• pp.45-53
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• 2002

The main idea behind the Intelligent Networks(IN) concept is the separation of switching functionality from the service control, in order to meet various service requirements of subscribers and development of new services in time. In (N+1) type Intelligent Network with FEP-BEP framwork, each SCP-BEP system maintains its own subscibers' database respectively. In this case, DB updating operations at each SCP-BEP should be peformed concurrently such that DB updating method could affect the overall system performance. Moreover, it is not easy to predict the current system capacity to satisfy the future IN subscribers' service needs. In this paper, we discuss how much DB updating method affects the performance trends of (N+1) type Intelligent Network with FEP-BEP system by means of the simulation technique as the number of calls increase. The average turnaround time is used as a system performance measure.

• Proceedings of the Korean Magnestics Society Conference
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• 2000.09a
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• pp.5-32
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• 2000

MRAM, High performance MRAM using MTJS demostrated, fully integrated MTJ MRAM with CMOS circuits, write time ~2.3 nsec; read time ~3 nsec, Thermally stable up to ~350 C, Switching field distibution controlled by size & shape. Magnetic Tunnel Junction Properties, Magnetoresistance: ~50% at room temperature, enhanced by thermal treatment, Negative and Positive MR by interface modification, Spin Polarization: >55% at 0.25K, Insensitive ot FM composition, Resistance $\times$ Area product, ranging from ~20 to 10$^{9}$ $\Omega$(${\mu}{\textrm}{m}$)$^{2}$, Spin valve transistor, Tunnel injected spin polarization for "hot" electrons, Decrease of MTJMR at high bias originates from anode.

• Korean Journal of Optics and Photonics
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• v.8 no.3
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• pp.218-222
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• 1997

We fabricated a bistable TN LCD with 180$^{\circ}$ twist angle and confirmed that it has a fast switching response time and a high contrast ratio. We also investigated the effects of the amplitude and width of the reset and selection pulses on a bistable TN LC cell and the conditions of the bistability and the memory time. The range of d/p values showing the bistability is determinded for the pretilt angle according to the rubbing depth.

• Journal of Communications and Networks
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• v.6 no.2
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• pp.147-155
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• 2004

In this paper, we propose an efficient sequencing technique, namely minimum Row time scheduling (MFTS), to manage variable-Iength message transmissions for single-hop passive starcoupled WDM optical networks. By considering not only the message length but also the state of the receivers and the tuning latency, the proposed protocol can reduce the average delay of the network greatly. This paper also introduces a new channel assignment technique latency minimizing scheduling (LMS), which aims to reduce the scheduling latency. We evaluate the proposed algorithm, using extensive discrete-event simulations, by comparing its performance with shortest job first (SJF) algorithm. We find that significant improvement in average delay could be achieved by MFTS algorithm. By combining the proposed message sequencing technique with the channel selection technique, the performance of the optical network could be further improved.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.1
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• pp.51-59
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• 1990

In this paper, a new variable structure control algorithm is proposed to reduce the reaching time on a phase plane. In the new method, a term proportional to the magnitude of the switching variables is added to the Morgan and Ozguners algorithm. When this algorithm is applied to second order systems the simulation results show that the new approach of the control algorithm is more effective than morgan's algorithm.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.9
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• pp.450-453
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• 2005

A high speed address recovery technique for AC plasma display panel(PDP) is proposed. Replacing GND switch by clamping diode. the recovery speed can be increased by saving GND hold-time and switching loss due to GND switch also becomes also be reduced. The proposed method is able to perform load-adaptive operation by controlling the voltage level of energy recovery capacitor, which prevents increasing inefficient power consumption caused by circuit loss during recovery operation. Test results with 50' HD single-scan PDP(resolution = 1366$\times$768) show that less than 3sons of recovery time is successfully accomplished and about$54\%$ of the maximum power consumption can be reduced, tracing minimum power consumption curves.