• Title/Summary/Keyword: time-space reconfiguration

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Effective Finite Element Modeling for a Large Mirror System Using Separated Node Connectivity (비공유 Node를 이용한 대구경 거울의 효율적인 유한요소 모델링)

  • Pyun, Jae-Won;Yang, Ho-Soon;Lee, Jong-Ung;Moon, Il Kweon
    • Korean Journal of Optics and Photonics
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    • v.28 no.6
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    • pp.304-313
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    • 2017
  • The finite element analysis for optimizing a mirror system consisting of a large-diameter mirror and flexures requires numerous, repetitive calculations and corrections of the actual model to satisfy the given design conditions. In general, modification of this real model is conducted by reconfiguring nodes of the elements. The reconfiguration is very time-consuming work, to fix the continuity of each of the newly formed component nodes at the interfaces. But the process is a very important factor in determining the analysis time. To save time in modeling and actual computation, and to attain faster convergence, we present a new opto-mechanical analysis using non-shared node connections at each of the interfaces of the optical components. By comparing the results between the new element model and a conventional element model with shared node connections, we found that the opto-mechanical performance was almost the same, but the time to reach the given condition was drastically reduced.

A Lower Bound Estimation on the Number of Micro-Registers in Time-Multiplexed FPGA Synthesis (시분할 FPGA 합성에서 마이크로 레지스터 개수에 대한 하한 추정 기법)

  • 엄성용
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.9
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    • pp.512-522
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    • 2003
  • For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Typically, the size of the chip required to implement the circuit depends on both the maximum number of the LUT blocks required to implement the function of each subcircuit and the maximum number of micro-registers to store results over context switches in the same time. Therefore, many partitioning or synthesis methods try to minimize these two factors. In this paper, we present a new estimation technique to find the lower bound on the number of micro-registers which can be obtained by any synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. If the estimated lower bound exactly matches the actual number in the actual design result, we can say that the result is guaranteed to be optimal. In contrast, if they do not match, the following two cases are expected: we might estimate a better (more exact) lower bound or we find a new synthesis result better than those of the previous work. Our experimental results show that there are some differences between the numbers of micro-registers and our estimated lower bounds. One reason for these differences seems that our estimation tries to estimate the result with the minimum micro-registers among all the possible candidates, regardless of usage of other resources such as LUTs, while the previous work takes into account both LUTs and micro-registers. In addition, it implies that our method may have some limitation on exact estimation due to the complexity of the problem itself in sense that it is much more complicated than LUT estimation and thus needs more improvement, and/or there may exist some other synthesis results better than those of the previous work.