• Title/Summary/Keyword: thin wafer

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Development of Real Time Thickness Measurement System of Thin Film for 12" Wafer Spin Etcher (12" 웨이퍼 Spin etcher용 실시간 박막두께 측정장치의 개발)

  • 김노유;서학석
    • Journal of the Semiconductor & Display Technology
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    • v.2 no.2
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    • pp.9-15
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    • 2003
  • This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12" silicon wafer for spin etcher. Halogen lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and adaptive filtering. Test wafers with three kinds of priori-known films, polysilicon(300 nm), silicon-oxide(500 nm) and silicon-oxide(600 nm), are measured while the wafer is spinning at 20 Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 0.8% error.rror.

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A Study on Various Parameters of the PE-CVD Chamber with Wafer Guide Ring (웨이퍼 가이드링 적용에 따른 PE-CVD 챔버 변수에 대한 연구)

  • Hyun-Chul Wang;Hwa-Il Seo
    • Journal of the Semiconductor & Display Technology
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    • v.23 no.2
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    • pp.55-59
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    • 2024
  • Plasma Enhanced Chemical Vapor Deposition (PE-CVD) is a widely used technology in semiconductor manufacturing for thin film deposition. The implementation of wafer guide rings in PE-CVD processes is crucial for enhancing efficiency and product quality by ensuring uniform deposition around wafer edges and reducing particle generation. On the other hand, to prevent overall temperature non-uniformity and degradation of thin film quality within the chamber, it is essential to consider various parameters comprehensively. In this study, after applying the wafer guide rings, temperature variations and fluid flow changes were simulated. Additionally, by simulating the temperature and flow changes when applied to the PE-CVD chamber, this paper discusses the importance of optimizing variables within the entire chamber.

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Phase transformation and magnetic properties of NiFe thin films on Si(100) wafer and SiO2/Si(100) substrate by co-sputtering (Si(100) wafer와 SiO2/Si(100) 기판에 동시 스퍼터링법으로 증착된 NiFe 합금 박막의 상변화 및 자기적 특성)

  • Kang, Dae-Sik;Song, Jong-Han;Nam, Joong-Hee;Cho, Jeong-Ho;Chun, Myoung-Pyo
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.20 no.5
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    • pp.216-220
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    • 2010
  • Ni-Fe alloys have various applications such as thin film inductor, thin film transformer, magnetic head's shield case, etc. Magnetic properties of Ni-Fe thin films depend on the process parameters such as thickness, contents, deposition rate, substrates, etc. In this study, NiFe films with a thickness of about 150nm were deposited on Si(100) wafer and $SiO_2$/Si(100) substrate at room temperature by a DC magnetron co-sputtering using Fe and Ni targets. Their phase formation and magnetic properties as a function of annealing temperature were investigated with XRD, FE-SEM and VSM. The assputtered films have BCC structure. With increasing annealing temperature, NiFe thin film for $SiO_2$/Si(100) substrate transformed completely from BCC to FCC phase above $500^{\circ}C$, but some BCC phase remained above $500^{\circ}C$ on Si(100) wafer. For samples annealed at $450^{\circ}C$, squareness ratio of NiFe thin film shows peak value and its saturation magnetization is around 0.0118 emu, which means that the optimum annealing temperature of NiFe thin film seems to be $450^{\circ}C$. The saturation magnetization of films decreased rapidly above the annealing temperature of $500^{\circ}C$ due to phase transformation from BCC to FCC phase.

Automated Wafer Separation from the Stacked Array of Solar Cell Silicon Wafers Using Continuous Water Jet

  • Kim, Kyoung-Jin;Kim, Dong-Joo;Kwak, Ho-Sang
    • Journal of the Semiconductor & Display Technology
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    • v.9 no.2
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    • pp.21-25
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    • 2010
  • In response to the industrial needs for automated handling of very thin solar cell wafers, this paper presents the design concept for the individual wafer separation from the stacked wafers by utilizing continuous water jet. The experimental apparatus for automated wafer separation was constructed and it includes the water jet system and the microprocessor controlled wafer stack advancing system. Through a series of tests, the performance of the proposed design is quantified into the success rate of single wafer separation and the rapidity of processing wafer stack. Also, the inclination angle of wafer equipped cartridge and the water jet flowrate are found to be important parameters to be considered for process optimization. The proposed design shows the concept for fast and efficient processing of wafer separation and can be implemented in the automated manufacturing of silicon based solar cell wafers.

Condition and New Testing Method of Interfacial Oxide Films in Directly Bonded Silicon Wafer Pairs (직접 접합된 실리콘 기판쌍에 있어서 계면 산화막의 상태와 이의 새로운 평가 방법)

  • ;;;;D.B. Murfett;M.R.Haskard
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.3
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    • pp.134-142
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    • 1995
  • We discovered that each distinct shape of the roof-shaped peaks of (111) facets, which are generated on (110) cross-section of the directly bonded (100) silicon wafer pairs after KOH etching, can be mapped to one of three conditions of the interfacial oxide existing at the bonding interface as follows. That is, thick solid line can be mapped to stabilization, thin solid line to disintegration, and thin broken line to spheroidization. also we confirmed that most of the interfacial oxides of a well-aligned wafer pairs were disintegrated and spheroidized through high-temperature annealing process above 900$^{\circ}$C while the oxide was stabilized persistently when two wafers are bonded rotationally around their common axis perpendicular to the wafer planes.

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Micro-bump Joining Technology for 3 Dimensional Chip Stacking (반도체 3차원 칩 적층을 위한 미세 범프 조이닝 기술)

  • Ko, Young-Ki;Ko, Yong-Ho;Lee, Chang-Woo
    • Journal of the Korean Society for Precision Engineering
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    • v.31 no.10
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    • pp.865-871
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    • 2014
  • Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

Analysis on Bowing and Formation of Al Doped P+ Layer by Changes of Thickness of N-type Wafer and Amount of Al Paste (N타입 결정질 실리콘 웨이퍼 두께 및 알루미늄 페이스트 도포량 변화에 따른 Bowing 및 Al doped p+ layer 형성 분석)

  • Park, Tae Jun;Byun, Jong Min;Kim, Young Do
    • Korean Journal of Materials Research
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    • v.25 no.1
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    • pp.16-20
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    • 2015
  • In this study, in order to improve the efficiency of n-type monocrystalline solar cells with an Alu-cell structure, we investigate the effect of the amount of Al paste in thin n-type monocrystalline wafers with thicknesses of $120{\mu}m$, $130{\mu}m$, $140{\mu}m$. Formation of the Al doped $p^+$ layer and wafer bowing occurred from the formation process of the Al back electrode was analyzed. Changing the amount of Al paste increased the thickness of the Al doped $p^+$ layer, and sheet resistivity decreased; however, wafer bowing increased due to the thermal expansion coefficient between the Al paste and the c-Si wafer. With the application of $5.34mg/cm^2$ of Al paste, wafer bowing in a thickness of $140{\mu}m$ reached a maximum of 2.9 mm and wafer bowing in a thickness of $120{\mu}m$ reached a maximum of 4 mm. The study's results suggest that when considering uniformity and thickness of an Al doped $p^+$ layer, sheet resistivity, and wafer bowing, the appropriate amount of Al paste for formation of the Al back electrode is $4.72mg/cm^2$ in a wafer with a thickness of $120{\mu}m$.

Design & development of a device for thin-film evaluation using a two-component loadcell (2축 로드셀을 이용한 박막평가장치의 설계 및 개발)

  • Lee, Jeong-Il;Kim, Jong-Ho;Park, Yon-Kyu;Oh, Hee-Geun
    • Proceedings of the KSME Conference
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    • 2003.11a
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    • pp.1448-1452
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    • 2003
  • A scratch tester was developed to evaluate the adhesive strength at interface between thin-film and substrate(silicon wafer). Under force control, the scratch tester can measure the normal and the tangential forces simultaneously as the probe tip of the equipment approaches to the interface between thin-film and substrate of wafer. The capacity of each component of force sensor is 0.1 N ${\sim}$ 100 N. In addition, the tester can detect the signal of elastic wave from AE sensor(frequency range of 900 kHz) attached to the probe tip and evaluate the bonding strength of interface. Using the developed scratch tester, the feasibility test was performed to evaluate the adhesive strength of thin-film.

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