• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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• pp.83-87
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• 2002

Plasma enhanced chemical vapor deposited (PECVD) silicon nitride ($SiN_X$) is widely used as a gate dielectric material for the hydrogenated amorphous silicon(a-Si:H) thin film transistors (TFT's). We investigated $SiN_X$ films were deposited PECVD at low temperature ($300^{\circ}C$). The reaction gases were used pure nitrogen and a helium diluted of silane gas(20% $SiH_4$, 80% He). Experimental investigations were carried out with the variation of $N_2/SiH_4$ flow ratios from 3 to 50 and the rf power of 200 W. This article presents the $SiN_X$ gate dielectric studies in terms of deposition rate, hydrogen content, etch rate and C-V, leakage current density characteristics for the gate dielectric layer of thin film transistor applications. Electrical properties were analyzed through high frequency (1MHz) C-V and current-voltage (I-V) measurements. The thickness and the refractive index on the films were measured by ellipsometry and chemical bonds were determined by using an FT-IR equipment.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.286-286
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• 2011

최근 폴리머를 기판으로 하는 Flexible TFT (thin film transistor)나 3D-ULSI (three dimensional ultra large-scale integrated circuit)에서 높은 에너지 소비효율과, 빠른 반응 속도를 실현 시키기 위해 낮은 비저항(resistivity)을 가지며, 높은 홀 속도(carrier hall mobility)를 가지는 다결정 반도체 박막(poly-crystalline thin film)을 만들고자 하고 있다. 이를 실현 시키기 위해서는 높은 온도에서 장시간의 열처리가 필요하며, 이는 폴리머 기판의 문제점을 야기시킬 뿐 아니라 공정시간이 길다는 단점이 있었다. 이에 반도체 박막의 재결정화 온도를 낮춰주는 metal (Al, Ni, Co, Cu, Ag, Pd etc.,)을 이용하여 결정화 시키는 방법이 많이 연구 되어지고 있지만, 이 또한 재결정화가 이루어진 반도체 박막 안에 잔여 금속(residual metal)이 존재하게 되어 비저항을 높이고, 홀 속도를 감소시키는 단점이 있다. 이에 본 실험은 HiPIMS (High power impulse magnetron sputtering)와 PIII and D (plasma immersion ion implantation and deposition) 공정을 복합시킨 프로세스로 적은양의 금속이온주입을 통하여 재결정화 온도를 낮췄을 뿐 아니라, 잔여 하는 금속의 양도 매우 적은 다결정 반도체 박막을 만들 수 있었다. 분석 장비로는 박막의 결정화도를 측정하기 위해 GAXRD (glancing angle X-ray diffractometer)를 사용하였고, 잔여 하는 금속의 양과 화학적 결합 상태를 알아보기 위해 XPS를 통해 분석을 하였다. 마지막으로 홀 속도와 비저항을 측정하기 위해 Hall measurement와 Four-point prove를 사용하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• 한국정보통신학회논문지
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• 제13권7호
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• pp.1393-1398
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• 2009

본 연구는 LCD용 비정질 실리콘박막트랜지스터의 제조공정중 가장 중요한 식각 공정에서 각 박막의 특성에 맞는 습식 및 건식식각공정을 개발하여 소자의 특성을 안정시키고자 한다. 본 연구의 수소화 된 비정질 실리콘 박막 트랜지스터는 Inverted Staggered 형태로 게이트 전극이 하부에 있다. 실험 방법은 게이트전극, 절연층, 전도층, 에치스토퍼 및 포토레지스터층을 연속 증착한다. 스토퍼층을 게이트 전극의 패턴으로 남기고, 그 위에 n+a-Si:H 층 및 NPR(Negative Photo Resister)을 형성시킨다. 상부 게이트 전극과 반대의 패턴으로 NPR층을 패터닝하여 그것을 마스크로 상부 n+a-Si:H 층을 식각하고, 남아있는 NPR층을 제거 한다. 그 위 에 Cr층을 증착한 후 패터닝 하여 소오스-드레인 전극을 위한 Cr층을 형성시켜 박막 트랜지스터를 제조한다. 여기서 각 박막의 패터닝은 식각 공정으로 각단위 박막의 특성에 맞는 건식 및 습식식각 공정이 필요하다. 제조한 박막 트랜지스터에서 가장 흔히 발생되는 문제는 주로 식각 공정시 over 및 under etching 이며, 정확한 식각을 위하여 각 박막에 맞는 식각공정을 개발하여 소자의 최적 특성을 제공하고자한다. 이와 같이 공정에 보다 엄격한 기준의 건식 및 습식식각 공정 그리고 세척 등의 처리공정을 정밀하게 실시하여 소자의 특성을 확실히 개선 할 수 있었다.

• 한국재료학회지
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• 제14권7호
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• pp.477-481
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• 2004

High quality polycrystalline silicon is very critical part of the high quality thin film transistor(TFT) for display devices. Metal induced lateral crystallization(MILC) is one of the most successful technologies to crystallize the amorphous silicon at low temperature(below $550^{\circ}C$) and uses conventional and large glass substrate. In this study, we observed that the MILC behavior changed with abrupt variation of the amorphous silicon active pattern width. We explained these phenomena with the novel MILC mechanism model. The 10 nm thick Ni layers were deposited on the glass substrate having various amorphous silicon patterns. Then, we annealed the sample at $550^{\circ}C$ with rapid thermal annealing(RTA) apparatus and measured the crystallized length by optical microscope. When MILC progress from narrow-width-area(the width was $w_2$) to wide-width-area(the width was $w_1$), the MILC rate decreased dramatically and was not changed for several hours(incubation time). Also the incubation time increased as the ratio, $w_1/w_2$, get larger. We can explain these phenomena with the tensile stress that was caused by volume shrinkage due to the phase transformation from amorphous silicon to crystalline silicon.

• 한국결정성장학회지
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• 제13권2호
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• pp.93-97
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• 2003

FALC(Field-Aided Lateral Crystallization) 공정에서 요구되는 a-Si의 결정화는 인가한 전계(electric field)의 세기와 방향에 의존한다. 본 연구에서는 유한요소법을 적용하여 실제 패턴을 간단하게 모델링한 형상에 각 물질의 전도도를 대입하고, 전안을 가해 그 결과로 발생하는 전계의 분포를 계산하였다. 전계는 (-)극 주위에서 전극의 양쪽 모서리 부근이 가운데 부분보다 더 높게 나타났고 그 방향은 전극과 50~$60^{\circ}$를 이루는 대각선 방향이었다. 또한 예상한대로 크기가 작은 패턴이 큰 패턴보다 더 큰 전계 값을 가지는 것으로 나타났다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1203-1207
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• 2008

For a large sized, ultra definition (UD) and high refresh rate for motion blur free AMLCD TVs, amorphous IGZO thin film transistor (TFT) are applied and investigated in terms of threshold voltage ($V_{th}$) shift influenced by active layer thickness uniformity, source drain etching technology, heat treatment and passivation condition. Optimizing above parameters, we fabricated the world's largest 15 inch XGA AMLCD successfully.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.553-556
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• 2008

We hereby report novel driving scheme to eliminate effect of "residual" image sticking (RRI) problem which arises due to hysteresis problem in Thin Film Transistor (TFT) in AMOLED Displays. The driving scheme applies "black" voltage after every data voltage period in order to drive AMOLED in uni-direction. The system can be easily implemented with 120 Hz driving scheme which is well matured in AMLCD industries. Our analyses show systematic evaluation of the problem and thereby solving it by simple methods which will be significantly effective of driving OLED towards mass manufacturing stage.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.295-298
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• 2003

Reflective mode liquid crystal on silicon (LCoS) microdisplay is the major technology that can produce extremely high-resolution displays. A very large number of pixels can be packed onto the CMOS circuit with integrated drivers that can be projected to any size screen. Large size direct-view thin film transistor (TFT) LCDs becomes very difficult to make and to drive as the information content increases. However, the existing LC alignment technology for the LCoS cell fabrication is still the mechanical rubbing method, which is prone to have minor defects that are not visible normally but can be detrimental if projected to a large screen. In this paper, application of photo-alignment to LCoS fabrication is presented. The alignment is done by three-step exposure process. A MTN $90^{\circ}$ mode is chose as to evaluate the performance of this technique. The comparison with rubbing mode shows the performance of photo-alignment is comparable and even better in some aspect, such as sharper RVC curve and higher contrast ratio.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2010년도 춘계학술발표대회
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• pp.19.1-19.1
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• 2010

The process of manufacturing printed electronics using printing technology is attracting attention because its process cost is lower than that of the conventional semiconductor process. This technology, which offers both a lower cost and higher productivity, can be applied in the production of organic TFT (thin film transistor), solar cell, RFID(radio frequency identification) tag, printed battery, E-paper, touch screen panel, black matrix for LCD(liquid crystal display), flexible display, and so forth. In general, in order to implement printed electronics, narrow width and gap printing, registration of multi-layer printing by several printing units, and printing accuracy of under $20\;{\mu}m$ are all required. These electronic products require high precision to the degree of tens of microns - in a large area with flexible material, and mass productivity at low cost. As such, the roll-to-roll printing process is attracting attention as a mass production system for these printed electronic devices. For the commercialization of this process, two basic electronic ink technologies, such as conductive ink and polymers, and printing equipment have to be developed. Therefore, this paper addressed basis design and test to develop fine patterning equipment employing the roll-to-roll printing equipment and electronic ink.