• Journal of Environmental Science International
• /
• v.7 no.5
• /
• pp.669-677
• /
• 1998

A porous $\alpha$-alumina tube of 2.5 mm O.D. and 1.9 mm I.D. was used as the support of an inorganic membrane. Macropores of the tube, about 150 nm in size, were plugged with silica formed by thermal decomposition of tetraethylorthosilicate at $600^{\circ}C$. The forced cross-flow CVD method that reactant was evacuated through the porous wall of the support was very effective in plugging macropores. The H$_2$ permeance of the prepared membrane was of the order of $10^{-8}/ molㆍs^{-1}/ㆍm^{-2}/. Pa{-1}$/, while the $N_2$ permeance was below $10^{-11}/ molㆍs^{-1}/ㆍm^{-2}/ㆍPa^{-1}$/ at $600^{\circ}C$. This was comparable to that of silica-modified Vycor glass whose size was 4 nm.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.20 no.5
• /
• pp.389-393
• /
• 2007

We fabricated field-effect transistor based carbon nanotubes(CNTs) directly grown by thermal chemical vapor deposition(CVD) and analyzed their performance. The Ethylene ($C_2H_4$), hydrogen($H_2$) and Argon(Ar) gases were used for the growth of CNTs at $700\;^{\circ}C$. The growth properties of CNTs on the device were analyzed by SEM and AFM. The electrical transport characteristics of CNT FET were investigated by I-V measurement. Transport through the nanotubes is dominated by holes at room temperature. By varying the gate voltage, we successfully modulated the conductance of FET device by more than 7 orders of magnitude.

• Journal of Sensor Science and Technology
• /
• v.16 no.4
• /
• pp.313-318
• /
• 2007

Single-wall carbon nanotube field-effect transistors (SWCNT FETs) of top gate structure were fabricated in a conventional metal-oxide-semiconductor field effect transistor (MOSFET) with gate electrodes above the conduction channel separated from the channel by a thin $SiO_{2}$ layer. The carbon nanotubes (CNTs) directly grown using thin Fe film as catalyst by thermal chemical vapor deposition (CVD). These top gate devices exhibit good electrical characteristics, including steep subthreshold slope and high conductance at low gate voltages. Our experiments show that CNTFETs may be competitive with Si MOSFET for future nanoelectronic applications.

• Korean Journal of Materials Research
• /
• v.1 no.1
• /
• pp.9-17
• /
• 1991

TiC coating formed on $Si_3N_4-TiC$ composite ceramic by chemical vapor deposition (CVD) has an improved microstructures, better thermal shock resistance and interfacial bonding than TiN coating does. TiN coating formed by CVD, however, has lower friction coefficients against steels and better chemical stability. The experimental results indicate that the coated insert is superior to the uncoated one in flank and crater wear resistance. And the multilayer coating shows an improved wear resistance than the monolayer coating.

• Proceedings of the KIEE Conference
• /
• 2000.11c
• /
• pp.440-442
• /
• 2000

We have successfully fabricated SiC Schottky diodes using Al, Ni, Ti metallization systems. Schottky barrier height and other parameter have been measured by using I-V and C-V technique. The measured barreir heights depend on the metal and measurement techniques used. The barrier heights were 1.85eV(Al), 1.63eV(Ni), 0.97eV(Ti). The Ideality factors were 1.16(Al), 1.07(Ni), 1.05(Ti). Thermal stress tests were performed.

• Journal of the Microelectronics and Packaging Society
• /
• v.4 no.2
• /
• pp.47-54
• /
• 1997

Pt/SiO2/Si을 기판으로 사용하고 RF 마그네트론 스퍼터링에 의한 (Ba, Sr)TiO3 (BST) 씨앗층을 약 10nm 정도의 두께로 입힌 다음 그 상부에 화학 기상증착법으로 BST를 증착하여 BST seed layer가 CVD BST 박막의 특성에 미치는 영향을 조사하였다. 또한 급 속열처리가 BST 박막과 커패시터의 특성에 미치는 영향도 조사하였다. Seed layer와 급속 열처리에 의해 박막의 결정성이 향상되었으며 이로인해 유전상수가 증가되었고 주파수에 대 한 유전특성도 개선되었다. Seed layer를 도입함으로써 BST 박막과 Pt 하부전극 사이의 계 면에 존재하고 있는 산소부족\ulcorner이 사라짐을 확인할수 있었으며 이로 인해 Pt/BST/Pt 커\ulcorner 시터의 누설전류가 감소하였다. 또한 급속 열처리에 의해 BST/Pt 계면에서 트랩된 전자의 농도가 감소함으로써 누설전류 특성이 개선됨을 알수 있었다. Seed layer 위에 증착된 CVD BST 박막의 유전상수는 증착온도가 증가함에 따라 증가하였으나 누설전류도 같이 증가하 였다.

• Journal of the Korean Ceramic Society
• /
• v.27 no.5
• /
• pp.645-651
• /
• 1990

Effects of excess Si on the properities of the oxide of CVD tungsten silicide were investigated by comparing the characteristics of the two kinds of thermal oxide for CVD-WSi2.7 and WSi3.1 films on the polycrystalline Si film each other. It is reveraled from AES analysis that Si in the surface region of the silicide film is consumed to make composition and resistivity of the silicide film very nonuniform for the case of the oxidation of WSi3.1, while the underlayer polycrystalline Si was consumed for the case of the oxidation of WSi2.7.

• Journal of the Korean institute of surface engineering
• /
• v.29 no.5
• /
• pp.577-584
• /
• 1996

Silicon oxide films with high hardness and water repellency were prepared by microwave plasma-enhanced CVD using four kind of organosilicon compound-fluoro-alkyl silane mixtures as source gases. An argon gas was used as a carrier gas for fluoro-alkyl silane. The substrate temperatures during deposition were controlled by resistant heating at a constant value between 50 and $300^{\circ}C$. The hardness of the films increased, but the deposition rate and the contact angle for a water drop decreased with increasing substrate temperature. The number of methoxy groups also affected the water repellency and hardness. The deposited films became more inorganic with increasing substrate temperature because of the thermal dissociation of reactants.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.212-212
• /
• 2016

2차원 탄소나노재료인 그래핀은 우수한 물성으로 인하여 광범위한 분야로 응용이 가능할 것으로 예상되어 많은 주목을 받아왔다. 이러한 그래핀의 응용가능성을 실현시키기 위해서는 보다 손쉽고 신뢰할 수 있는 합성방법의 개발이 필요한 실정이다. 그래핀의 합성 방법들로 흑연을 물리적 및 화학적으로 박리하거나, 특정 결정표면 위에 방향성 성장의 흑연화를 통한 합성, 그리고 열화학기상증착법(Thermal chemical vapor deposition; T-CVD) 등의 합성방법들이 제기되었다. 이중 T-CVD법은 대면적으로 두께의 균일성이 높은 그래핀을 합성하기 위한 가장 적합한 방법으로 알려져 있다. 그러나 일반적으로 T-CVD공정은 원료 가스인 탄화수소가스를 효율적으로 분해하기 위하여 $1000^{\circ}C$부근의 온공정이 요구되며, 이는 산업적인 응용의 측면에서 그래핀의 접근성을 제한한다. 따라서 대면적으로 고품질의 그래핀을 저온합성 할 수 있는 공정의 개발은 필수적이다. 본 연구에서는, 플라즈마를 이용하여 원료가스를 효율적으로 분해함으로써 그래핀의 저온합성을 도모하였다. 퀄츠 튜브로 구성된 수평형 합성장치는 플라즈마 방전영역과 T-CVD 영역으로 구분되며, 방전되는 유도결합 플라즈마는 원료가스를 효율적으로 분해하는 역할을 한다. 합성을 위한 기판과 원료가스로는 각각 전자빔 증착법을 통하여 300nm 두께의 니켈 박막이 증착된 실리콘 웨이퍼와 메탄가스를 이용하였다. 저온합성공정의 변수로는 인가전력과 합성시간으로 설정하였으며, 공정변수의 영향을 확인함으로써 그래핀의 저온합성 메커니즘을 고찰하였다. 연구결과, 인가전력이 증가되고 합성시간이 길어짐에 따라 원료가스의 분해효율과 공급되는 탄소원자의 반응시간이 보장되어 그래핀의 합성온도가 저하가능함을 확인하였으며, $400^{\circ}C$에서 다층 그래핀이 합성됨을 확인하였다. 또한 플라즈마 변수의 보다 정밀한 제어를 통해 합성온도의 저온화와 그래핀의 결정성 향상이 가능할 것으로 예상된다.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2011.10a
• /
• pp.16.2-16.2
• /
• 2011

Graphene has attracted significant attention due to its unique characteristics and promising nanoelectronic device applications. For practical device applications, it is essential to synthesize high-quality and large-area graphene films. Graphene has been synthesized by eloborated mechanical exfoliation of highly oriented pyrolytic graphite, chemical reduction of exfoliated grahene oxide, thermal decomposition of silicon carbide, and chemical vapor deposition (CVD) on metal substrates such as Ni, Cu, Ru etc. The CVD has advantages over some of other methods in terms of mass production on large-areas substrates and it can be easily separated from the metal substrate and transferred to other desired substrates. Especially, plasma-enhanced CVD (PECVD) can be very efficient to synthesize high-quality graphene. Little information is available on the synthesis of graphene by PECVD even though PECVD has been demonstrated to be successful in synthesizing various carbon nanostructures such as carbon nanotubes and nanosheets. In this study, we synthesized graphene on $Ni/SiO_2/Si$ and Cu plate substrates with CH4 diluted in $Ar/H_2$ (10%) by using an inductively-coupled PECVD (ICPCVD). High-quality graphene was synthesized at as low as $700^{\circ}C$ with 600 W of plasma power while graphene layer was not formed without plasma. The growth rate of graphene was so fast that graphene films fully covered on substrate surface just for few seconds $CH_4$ gas supply. The transferred graphene films on glass substrates has a transmittance at 550 nm is higher 94%, indicating 1~3 monolayers of graphene were formed. FETs based on the grapheme films transferred to $Si/SiO_2$ substrates revealed a p-type. We will further discuss the synthesis of graphene and doped graphene by ICPVCD and their characteristics.