• Journal of Internet Computing and Services
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• v.2 no.1
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• pp.1-11
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• 2001

Though it is proposed to use Petri net or dynamic FSM methods for the generation of test sequences on some specific protocols, those methods ere unavailable on the cases where the protocol allows faults processing or includes paths in looping which cause errors or endless looping by the explosion of states. The determination of test coverage on the protocol software that has been designed and implemented is difficult by the reason of development periods, technical solutions to support and also economical limitations. It is suggested to generate timely protocol software test sequences on the basis of regular expressions covering the functions of protocol. With this regular expression method, the 38 test sequences of Q.2971 protocol has been generated and also minimized the endless looping problem when dynamic test suites are used by simplifying the test path expressions that denotes loops, According to the works, the suggested method is confirmed as simple and easy compare to the other dynamic test sequence generation techniques. Moreover. the method to search an optional test path whether it Is included or not in the regular path expression is reviewed.

• Journal of the Korean Society of Environmental Restoration Technology
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• v.8 no.3
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• pp.13-20
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• 2005

This study was conducted to suggest the ecological restoration methods of the decomposed granite cut-slope by organic soil amendment materials. Field test carried out for the cut-slope with organic soil amendment materials method and other three revegetation methods in Cheongwon. Test revegetation plants were Festuca arundinacea, Lolium perenne, Dactylis glomerata, Lespedeza cyrtobotrya, and Arundinella hirta. The result of this study can be summarized as follows; 1. The soil hardness, the soil acidity, and the soil humidity of organic soil amendment materials method were at a suitable value for plants growth. And it was better as compared with other three revegetation methods of cutting-rock slopes. 2. The result of toxic substance investigation, all items were at a suitable for standard law. 3. During one year after seeding, most plants germinated and especially Festuca arundinacea and Dactylis glomerata grows well. Seedling numbers were 336.7 per $m^2$(after 6 months), 183.3 per $m^2$(after 10 months), and 353.3 per $m^2$(after 6 months). Ten months later after seeding, plants showed 80% ground coverage. Visual rate, plant height, and growth rate were excellence, Also, high plant growth in spring better than autumn.

• Nuclear Engineering and Technology
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• v.52 no.7
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• pp.1462-1470
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• 2020

Reliability in safety-critical systems and equipment is of vital importance, so the probabilistic safety assessment (PSA) has been widely used for many years in the nuclear industry to address reliability in a quantitative manner. As many nuclear power plants (NPPs) become digitalized, evaluating the reliability of safety-critical software has become an emerging issue. Due to a lack of available methods, in many conventional PSA models only hardware reliability is addressed with the assumption that software reliability is perfect or very high compared to hardware reliability. This study focused on developing a new method of safety-critical software reliability quantification, derived from hardware-software integrated environment testing. Since the complexity of hardware and software interaction makes the possible number of test cases for exhaustive testing well beyond a practically achievable range, an importance-oriented testing method that assures the most efficient test coverage was developed. Application to the test of an actual NPP reactor protection system demonstrated the applicability of the developed method and provided insight into complex software-based system reliability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.74-84
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• 2003

Conventional test algorithms do not effectively detect faults by word-line and bit-line coupling noise resulting from the increase of the density of memories. In this paper, the possibility of faults caused by word-line coupling noise is shown, and new fault model, WLSFs(Word-Line Sensitive Fault) is proposed. We also introduce the algorithm considering both word-line and bit-line coupling noise simultaneously. The algorithm increases probability of faults which means improved fault coverage and more effective test algorithm, compared to conventional ones. The proposed algorithm can also cover conventional basic faults which are stuck-at faults, transition faults and coupling faults within a five-cell physical neighborhood.

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1633-1638
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• 1998

In this paper we propose a generic BIST builder for the Embedded Multiple HAM modules in ASICs, The BlST circuitry is automatically generated according to the specification of the target RAM Modules and the applying test algorithms to them. The lJIST is designed using the TOP-DOWN technique and, thus, has the several advantages in the area of the selection of test algorithm, the development of the circuitry, and the reuse of the circuitry, In addition, we have modified the existing serial interiacing approach to obtain smaller additional BlST circuitry and higher fault coverage and better B1ST sharing of the target RAM Modules in ASICs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.30-37
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• 2006

This paper presents a modified scan cell architecture to reduce the power dissipation during testing. It not only eliminates switching activities in the combinational logic during scan shifting but also reduces switching activities in the scan chain during the time. Furthermore, it limits the transitions on capture cycles. It can be made for test-per-scan BIST and employed in both single scan style and multiple scan style. Experimental results demonstrate that the proposed structure achieves the same fault coverage with lower power consumption compared to other existing BIST schemes.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.43-51
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• 2001

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased. And testing high-density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. So far, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new test algorithm for neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs(Neighborhood Pattern Sensitive Faults) is proposed. And the proposed algorithm does not require any additional circuit. Instead of the conventional five-cell or nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. Furthermore, to consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e.,$write{\rightarrow}\;refresh{\rightarrow}\;read$). Also, we show that the proposed algorithm can detect stuck-at faults, transition faults, coupling faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• Journal of The Korea Institute of Healthcare Architecture
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• v.25 no.3
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• pp.75-83
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• 2019

Purpose: There are no clear criteria for slip performance in the BF certification process, so the evaluator relies on subjective judgments depending on the field situation. Physical criteria for determining the slip performance of various floor finishes are not clear. C.S.R., the only criterion currently being used to check slip performance, may raise questions about its coverage, feasibility and reliability. Method: For an analysis of domestic standards and status, KS L 1001, KS M 3510, and KS F 2375. External standards are analyzed for ADA Standard, ANSI Standard, and BS EN Standard. Analyze the test methods and evaluation criteria of O-Y-PSM, BPT, and the dynamic slip resistance test used in these criteria. It also presents an improvement plan for the rational presentation of standards. Results: To date, various kinds of test methods and measuring devices of the slip resistance coefficient have been developed, but there are not many ways to trust useful results related to user safety. Reliability and thoroughly verified test methods and criteria should be used to assess the slip performance of the floor. In order to improve the standard for the evaluation of slip performance in Korea, the existing standard should first be raised to the same level as the overseas standard, and the application of the discriminatory standard should be applied considering the characteristics and usage patterns of each space. Implication: Currently, Korean standards propose various test methods, but the proper use of test methods, scope and assessment criteria are not established, so improvement of the comprehensive standard is necessary.

• Journal of Advanced Navigation Technology
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• v.27 no.2
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• pp.228-234
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• 2023

As the increasing demand for high-quality software, there is huge requiring for quality certification of international standards, industrial functional safety (IEC 61508), automotive (ISO 26262), embedded software guidelines for weapon systems, etc., in the industry. Software companies are very difficult to systematically acquire the quality certification in terms of cost and manpower of Startup, venture small-sized companies. For their companies one test case automatic generation is considered as a core technique to evaluate or improve software quality. This paper proposes a test case automatic generation method based on the design decision table for system and software design verification. We apply the proposed method with OMG's standard techniques of metamodel and model transformation for automatically generating test cases. To do this, we design the metamodels of design decision table (Model) and test case document (Text) and define model transformation to automatically generate test cases, which will expect to easily work MC/DC coverage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.43-48
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• 2008

Power consumption during test can be much higher than that during normal operation since test vectors are determined independently. In order to reduce the power consumption during test process, a new BIST(Built-In Self Test) architecture is proposed. In the proposed architecture, test vectors generated by an LFSR(Linear Feedback Shift Resister) are transformed into the new patterns with low transitions using Bit Generator and Bit Dropper. Experiments performed on ISCAS'89 benchmark circuits show that transition reduction during scan testing can be achieved by 62% without loss of fault coverage. Therefore the new architecture is a viable solution for reducing both peak and average power consumption.