• Journal of the Society of Naval Architects of Korea
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• v.57 no.5
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• pp.262-270
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• 2020

An outdoor free-running model test system was designed for assessing ship maneuverability with test uncertainty. The test model was a surface combatant of tumblehome hull geometry. The straight forward tests were conducted first to obtain the relationship between the propeller revolution rate and advance speed. During the outdoor tests, the propeller revolution rate to achieve a certain Froude number condition was higher than that in the indoor free-running model tests. Turning circle and zigzag tests for evaluating ship maneuverability criteria were carried out at the propeller revolution rate determined by the straight forward test results. The random and systematic standard uncertainties of maneuvering criteria were obtained by repeated tests and comparison with the indoor free-running model test results, respectively. The test uncertainty was largely dominated by the systematic standard uncertainty, while the random standard uncertainty was small with good repeatability.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.293-296
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• 2012

SOC test methodology in ultra deep submicron (UDSM) technology with reasonable test time and cost has begun to satisfy high quality and reliability of the product. A novel hierarchical test architecture using IEEE standard 1149.1, 1149.7 and 1500 compliant facilities is proposed for the purpose of supporting flexible test environment to ensure SOC test methodology. Each embedded core in a system-on- a-chip (SOC) is controlled by test access ports (TAP) and TAP controller of IEEE standard 1149.1 as well as tested using IEEE standard 1500. An SOC device including TAPed cores is hierarchically organized by IEEE standard 1149.7 in wafer and chip level. As a result, it is possible to select/deselect all cores embedded in an SOC flexibly and reduce test cost dramatically using star scan topology.

• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.13-21
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• 2010

IEEE 1149.1 test architecture was proposed to support the test of elements within the boards. It is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. Even though it performs the board level test perfectly, there is a problems of running system level test when the boards are equipped to the system. To test real time operation signal on test pin, output speed of serial shift register chain must be above double clock speed of shift register. In this paper, we designed a runtime test architecture and a runtime test procedure under running system environments to capture runtime signal at system clock rate. The suggested runtime test architecture are simulated by Altera Max+Plus 10.0. through the runtime test procedure. The simulation results show that operations of the suggested runtime test architecture are very accurate.

• Journal of Korean Association for Spatial Structures
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• v.20 no.3
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• pp.43-52
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• 2020

In this study, the Buckling restrained braces reinforced with engineering plastics that can compensate for the disadvantages in the manufacturing process of the existing buckling restrained brace. The proposed PC-BRB was fabricated to evaluate the reinforcement effect by carrying out a structural performance test and a full-scale two-layer frame test through cyclic loading test. As a result of PC-BRB's incremental and cyclic loading test, stable hysteresis behavior was achieved within the target displacement, and the compressive strength adjustment coefficient satisfied the recommendation. As a result of the real frame experiment, the strength of the reinforced specimen increased compared to the unreinforced specimen, and the ductility and energy dissipation increased.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.259-262
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• 2013

Multi-site testing is considered as a solution to reduce test costs. This paper presents a new channel sharing architecture that enables I/O pins to share automatic test equipment (ATE) channels using simple circuitry such as tri-state buffers, AND gates, and multiple-input signature registers (MISR). The main advantage of the proposed architecture is that it is implemented on probe cards and does not require any additional circuitry on a target device under test (DUT). In addition, the proposed architecture can perform DC parametric testing of the DUT such as leakage testing, even if the different DUTs share the same ATE channels. The simulation results show that the proposed architecture is very efficient and is applicable to both wafer testing and package testing.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.10
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• pp.1081-1087
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• 2008

This paper describes limitations and solutions of the existing processor-monitoring concept for a military supersonics aircraft Flight Control Computer (FLCC) equipped with modern architecture processor to perform the system integration test. Safecritical FLCC integration test, which requires automatic test for thousands of test cases and real-time input/output test condition generation, depends on the processor-monitoring device called Processor Interface (PI). The PI, which relies upon on the FLCC processor's external address and data-bus data, has some limitations due to multi-fetching capability of the modern sophisticated military processors, like C6000's VLIW (Very-Long Instruction Word) architecture and PowerPC's Superscalar architecture. Several techniques for limitations were developed and proper monitoring approach was presented for modem processor-adopted FLCC system integration test.

• ETRI Journal
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• v.10 no.2
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• pp.3-12
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• 1988

Several ISDN (Integrated Services Digital Network) protocols have implemented at ETRI (Electronics and Telecommunications Research Institute) in an experimental network so that functional characteristics of the protocols under test could be certified against their protocol specifications with the help of the ETRI protocol test facilities. This paper describes ETRI protocol test architecture and its application to testing the NSP (Network Service Part) protocols : MTP (Message Transfer Part) level 3 and SCCP (Signalling Connection Control Part) of the CCITT CCS (Common Channel Signalling ) system No. 7 The test architecture presented here allows tests for two different protocol classes : peer-to-peer and multipeer protocolos. Some extensions are made to the conventional test architectures, namely the test coordination, test result transfer and network state observation method.

• Journal of Korea Game Society
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• v.7 no.3
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• pp.31-38
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• 2007

In this paper, we proposed an effective visibility test architecture with improving the mid-texturing architecture. The proposed architecture uses the property of fragments that the visibility of adjacent fragments is identical, and performs only a single visibility test per fragment. To compare with the mid-texturing architecture, simulation results show that the bandwidth requirements and the cell area of the depth cache in the proposed architecture are reduce by 25% and 34%, respectively, in exchange for less than 5% performance decline.

• International Journal of Naval Architecture and Ocean Engineering
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• v.7 no.4
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• pp.720-738
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• 2015

This study examined the dynamic response of a subsea pipeline under an impact load to determine the effect of the seabed soil. A laboratory-scale soil-based pipeline impact test was carried out to investigate the pipeline deformation/strain as well as the interaction with the soil-pipeline. In addition, an impact test was simulated using the finite element technique, and the calculated strain was compared with the experimental results. During the simulation, the pipeline was described based on an elasto-plastic analysis, and the soil was modeled using the Mohr-Coulomb failure criterion. The results obtained were compared with ASME D31.8, and the differences between the analysis results and the rules were specifically investigated. Modified ASME formulae were proposed to calculate the precise structural behavior of a subsea pipeline under an impact load when considering sand- and clay-based seabed soils.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.217-230
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• 2012

This paper propose interacting test programming methods between test equipment and hardware unit to verify function and performance of the hardware unit under test. Proposed test program can minimizes the risk of failures when the unit is mounted on the aircraft by testing and verifying the unit under the worst stress condition. Also, Object oriented design using UML make it easy to apply in other equipments. Test program consists of architecture package and hardware package. Architecture package is in a role for system management, log analysis, message receiving and message analysis. Messages that are used by system management define messages for testing and defined messages is sent and received to test equipment through Ethernet. Hardware package is in a role for hardware management that is needed to be tested and is related to a system. Hardware to be tested is divided into internal test and transmission test. Internal test inspects hardware itself and reports the test results to the test equipment. Transmission test inspects communication device by sending or receiving data. All kinds of test is done in the worst condition of the test unit executing in parallel. Each device is tested at least 482 times and at most 15,003 times about one hour. Test program is utilized in hardware reliability test like as environmental test or EMI test.