• Title/Summary/Keyword: systems-theory

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Design and Implementation of Service based Virtual Screening System in Grids (그리드에서 서비스 기반 가상 탐색 시스템 설계 및 구현)

  • Lee, Hwa-Min;Chin, Sung-Ho;Lee, Jong-Hyuk;Lee, Dae-Won;Park, Seong-Bin;Yu, Heon-Chang
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.6
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    • pp.237-247
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    • 2008
  • A virtual screening is the process of reducing an unmanageable number of compounds to a limited number of compounds for the target of interest by means of computational techniques such as molecular docking. And it is one of a large-scale scientific application that requires large computing power and data storage capability. Previous applications or softwares for molecular docking such as AutoDock, FlexX, Glide, DOCK, LigandFit, ViSION were developed to be run on a supercomputer, a workstation, or a cluster-computer. However the virtual screening using a supercomputer has a problem that a supercomputer is very expensive and the virtual screening using a workstation or a cluster-computer requires a long execution time. Thus we propose a service-based virtual screening system using Grid computing technology which supports a large data intensive operation. We constructed 3-dimensional chemical molecular database for virtual screening. And we designed a resource broker and a data broker for supporting efficient molecular docking service and proposed various services for virtual screening. We implemented service based virtual screening system with DOCK 5.0 and Globus 3.2 toolkit. Our system can reduce a timeline and cost of drug or new material design.

Buffer Cache Management for Low Power Consumption (저전력을 위한 버퍼 캐쉬 관리 기법)

  • Lee, Min;Seo, Eui-Seong;Lee, Joon-Won
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.6
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    • pp.293-303
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    • 2008
  • As the computing environment moves to the wireless and handheld system, the power efficiency is getting more important. That is the case especially in the embedded hand-held system and the power consumed by the memory system takes the second largest portion in overall. To save energy consumed in the memory system we can utilize low power mode of SDRAM. In the case of RDRAM, nap mode consumes less than 5% of the power consumed in active or standby mode. However hardware controller itself can't use this facility efficiently unless the operating system cooperates. In this paper we focus on how to minimize the number of active units of SDRAM. The operating system allocates its physical pages so that only a few units of SDRAM need to be activated and the unnecessary SDRAM can be put into nap mode. This work can be considered as a generalized and system-wide version of PAVM(Power-Aware Virtual Memory) research. We take all the physical memory into account, especially buffer cache, which takes an half of total memory usage on average. Because of the portion of buffer cache and its importance, PAVM approach cannot be robust without taking the buffer cache into account. In this paper, we analyze the RAM usage and propose power-aware page allocation policy. Especially the pages mapped into the process' address space and the buffer cache pages are considered. The relationship and interactions of these two kinds of pages are analyzed and exploited for energy saving.

Color Media Instructions for Embedded Parallel Processors (임베디드 병렬 프로세서를 위한 칼라미디어 명령어 구현)

  • Kim, Cheol-Hong;Kim, Jong-Myon
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.7
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    • pp.305-317
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    • 2008
  • As a mobile computing environment is rapidly changing, increasing user demand for multimedia-over-wireless capabilities on embedded processors places constraints on performance, power, and sire. In this regard, this paper proposes color media instructions (CMI) for single instruction, multiple data (SIMD) parallel processors to meet the computational requirements and cost goals. While existing multimedia extensions store and process 48-bit pixels in a 32-bit register, CMI, which considers that color components are perceptually less significant, supports parallel operations on two-packed compressed 16-bit YCbCr (6 bit Y and 5 bits Cb, Cr) data in a 32-bit datapath processor. This provides greater concurrency and efficiency for YCbCr data processing. Moreover, the ability to reduce data format size reduces system cost. The reduction in data bandwidth also simplifies system design. Experimental results on a representative SIMD parallel processor architecture show that CMI achieves an average speedup of 6.3x over the baseline SIMD parallel processor performance. This is in contrast to MMX (a representative Intel's multimedia extensions), which achieves an average speedup of only 3.7x over the same baseline SIMD architecture. CMI also outperforms MMX in both area efficiency (a 52% increase versus a 13% increase) and energy efficiency (a 50% increase versus an 11% increase). CMI improves the performance and efficiency with a mere 3% increase in the system area and a 5% increase in the system power, while MMX requires a 14% increase in the system area and a 16% increase in the system power.

Embedding Algorithm among Folded Hypercube, Even Network and Odd Network (폴디드 하이퍼큐브와 이븐연결망, 오드연결망 사이의 임베딩 알고리즘)

  • Kim, Jong-Seok;Sim, Hyun;Lee, Hyeong-Ok
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.7
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    • pp.318-326
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    • 2008
  • In this paper, we will analyze embedding among Folded Hypercube, Even Network and Odd Network to further improve the network cost of Hypercube. We will show Folded Hypercube $FQ_n$ can be embedded into Even Network $E_{n-1}$ with dilation 2, congestion 1 and Even Network $E_d$ can be embedded into Folded Hypercube $FQ_{2d-3}$ with dilation 1. Also, we will prove Folded Hypercube $FQ_n$ can be embedded into Odd Network $O_{n-1}$ with dilation 2, congestion 1 and Odd Network $O_d$ can be embedded into Folded Hypercube $FQ_{2d-3}$ with dilation 2, congestion 1. Finally, we will show Even Network $E_d$ can be embedded into Odd Network $O_d$ with dilation 2, congestion 1 and Odd Network $O_d$ can be embedded into Folded Hypercube $E_{d-1}$ with dilation 2, congestion 1.

Design of Music Recommendation System Considering Context-Information in the Home Network (홈 네트워크에서 상황정보를 고려한 음악 추천 시스템 설계)

  • Song Chang-Woo;Kim Jomg-Hun;Lee Jung-Hyun
    • Journal of KIISE:Computer Systems and Theory
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    • v.33 no.9
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    • pp.650-657
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    • 2006
  • The music is a part of our daily life in these days. And when the people listen to the music, they are affected by the context. However, previous researches on the music recommendation system have the problem that they didn't consider the proper contextual information efficiently. They only used the content-based filtering or the method to use musical metadata (genre, artist, etc.). Recently, there are some researches about the music recommendation system which applies the status(temperature, humidity, etc.) of environments. But, it is difficult to be accepted by the contextual information. Therefore, we propose the music recommendation system that is dynamically applied by the contextual information as well as the metadata in the previous researches. And the system can provide users with the music that they want to listen to, and then the users can be more satisfied. Also, the services can be improved by the feedback of the users. In order to solve this problem, the context-information for selecting a music list is defined and the music recommendation system is designed by using the content-based filtering method. The system is suitable for the user's taste and the context. The music recommendation system we are proposing uses an OSGi framework in the home network. As a result, the satisfaction of users and the quality of services will be improved more efficiently by supporting the mobility of services as well as the distributed processing.

Hardware-Software Cosynthesis of Multitask Multicore SoC with Real-Time Constraints (실시간 제약조건을 갖는 다중태스크 다중코어 SoC의 하드웨어-소프트웨어 통합합성)

  • Lee Choon-Seung;Ha Soon-Hoi
    • Journal of KIISE:Computer Systems and Theory
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    • v.33 no.9
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    • pp.592-607
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    • 2006
  • This paper proposes a technique to select processors and hardware IPs and to map the tasks into the selected processing elements, aming to achieve high performance with minimal system cost when multitask applications with real-time constraints are run on a multicore SoC. Such technique is called to 'Hardware-Software Cosynthesis Technique'. A cosynthesis technique was already presented in our early work [1] where we divide the complex cosynthesis problem into three subproblems and conquer each subproblem separately: selection of appropriate processing components, mapping and scheduling of function blocks to the selected processing component, and schedulability analysis. Despite good features, our previous technique has a serious limitation that a task monopolizes the entire system resource to get the minimum schedule length. But in general we may obtain higher performance in multitask multicore system if independent multiple tasks are running concurrently on different processor cores. In this paper, we present two mapping techniques, task mapping avoidance technique(TMA) and task mapping pinning technique(TMP), which are applicable for general cases with diverse operating policies in a multicore environment. We could obtain significant performance improvement for a multimedia real-time application, multi-channel Digital Video Recorder system and for randomly generated multitask graphs obtained from the related works.

Bus Splitting Techniques for MPSoC to Reduce Bus Energy (MPSoC 플랫폼의 버스 에너지 절감을 위한 버스 분할 기법)

  • Chung Chun-Mok;Kim Jin-Hyo;Kim Ji-Hong
    • Journal of KIISE:Computer Systems and Theory
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    • v.33 no.9
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    • pp.699-708
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    • 2006
  • Bus splitting technique reduces bus energy by placing modules with frequent communications closely and using necessary bus segments in communications. But, previous bus splitting techniques can not be used in MPSoC platform, because it uses cache coherency protocol and all processors should be able to see the bus transactions. In this paper, we propose a bus splitting technique for MPSoC platform to reduce bus energy. The proposed technique divides a bus into several bus segments, some for private memory and others for shared memory. So, it minimizes the bus energy consumed in private memory accesses without producing cache coherency problem. We also propose a task allocation technique considering cache coherency protocol. It allocates tasks into processors according to the numbers of bus transactions and cache coherence protocol, and reduces the bus energy consumption during shared memory references. The experimental results from simulations say the bus splitting technique reduces maximal 83% of the bus energy consumption by private memory accesses. Also they show the task allocation technique reduces maximal 30% of bus energy consumed in shared memory references. We can expect the bus splitting technique and the task allocation technique can be used in multiprocessor platforms to reduce bus energy without interference with cache coherency protocol.

Design of Software and Hardware Modules for a TCP/IP Offload Engine with Separated Transmission and Reception Paths (송수신 분리형 TCP/IP Offload Engine을 위한 소프트웨어 및 하드웨어 모듈의 설계)

  • Jang Hank-Kok;Chung Sang-Hwa;Choi Young-In
    • Journal of KIISE:Computer Systems and Theory
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    • v.33 no.9
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    • pp.691-698
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    • 2006
  • TCP/IP Offload Engine (TOE) is a technology that processes TCP/IP on a network adapter instead of a host CPU to reduce protocol processing overhead from the host CPU. There have been some approaches to implementing TOE: software TOE based on an embedded processor; hardware TOE based on ASIC implementation; and hybrid TOE in which software and hardware functions are combined. In this paper, we designed software modules and hardware modules for a hybrid TOE on an FPGA that had two processor cores. Software modules are based on the embedded Linux. Hardware modules are for data transmission (TX) and reception (RX). One core controls the TX path and the other controls the RX path of the Linux. This TX/RX path separation mechanism can reduce task switching overheads between processes and overcome poor performance of single embedded processor. Hardware modules deal with creating headers for outgoing packets, processing headers of incoming packets, and fetching or storing data from or to the host memory by DMA. These can make it possible to improve the performance of data transmission and reception. We proved performance of the TOE with separated transmission and reception paths by performing experiments with a TOE network adapter that was equipped with the FPGA having processor cores.

Sintering Mixtures in the Stage of Establishing Chemical Equilibrium

  • Savitskii, A.P.
    • Proceedings of the Korean Powder Metallurgy Institute Conference
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    • 1999.04a
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    • pp.5-5
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    • 1999
  • The Principal deficiency of the existing notion about the sintering-mixtures consists in the fact that almost no attention is focused on the Phenomenon of alloy formation during sintering, its connection with dimensional changes of powder bodies, and no correct ideas on the driving force for the sintering process in the stage of establishing chemical equilibrium in a system are available as well. Another disadvantage of the classical sintering theory is an erroneous conception on the dissolution mechanism of solid in liquid. The two-particle model widely used in the literature to describe the sintering phenomenon in solid state disregards the nature of the neighbouring surrounding particles, the presence of pores between them, and the rise of so called arch effect. In this presentation, new basic scientific principles of the driving forces for the sintering process of a two-component powder body, of a diffusion mechanism of the interaction between solid and liquid phases, of stresses and deformation arising in the diffusion zone have been developed. The major driving force for sintering the mixture from components capable of forming solid solutions and intermetallic compounds is attributed to the alloy formation rather than the reduction of the free surface area until the chemical equilibrium is achieved in a system. The lecture considers a multiparticle model of the mixed powder-body and the nature of its volume changes during solid-state and liquid-phase sintering. It explains the discovered S-and V-type concentration dependencies of the change in the compact volume during solid-state sintering. It is supposed in the literature that the dissolution of solid in liquid is realised due to the removal of atoms from the surface of the solid phase into the melt and then their diffusicn transfer from the solid-liquid interface into the bulk of liquid. It has been shown in our experimental studies that the mechanism of the interaction between two components, one of them being liquid, consist in diffusion of the solvent atoms from the liquid into the solid phase until the concentration of solid solutions or an intermetallic compound in the surface layer enables them to pass into the liquid by means of melting. The lecture discusses peculimities of liquid phase formation in systems with intermediate compounds and the role of the liquid phase in bringing about the exothermic effect. At the frist stage of liquid phase sintering the diffusion of atoms from the melt into the solid causes the powder body to grow. At the second stage the diminution of particles in size as a result of their dissolution in the liquid draws their centres closer to each other and makes the compact to shrink Analytical equations were derived to describe quantitatively the porosity and volume changes of compacts as a result of alloy formation during liquid phase sinteIing. Selection criteria for an additive, its concentration and the temperature regime of sintering to control the density the structure of sintered alloys are given.

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Stereo Image-based 3D Modelling Algorithm through Efficient Extraction of Depth Feature (효율적인 깊이 특징 추출을 이용한 스테레오 영상 기반의 3차원 모델링 기법)

  • Ha, Young-Su;Lee, Heng-Suk;Han, Kyu-Phil
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.10
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    • pp.520-529
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    • 2005
  • A feature-based 3D modeling algorithm is presented in this paper. Since conventional methods use depth-based techniques, they need much time for the image matching to extract depth information. Even feature-based methods have less computation load than that of depth-based ones, the calculation of modeling error about whole pixels within a triangle is needed in feature-based algorithms. It also increase the computation time. Therefore, the proposed algorithm consists of three phases, which are an initial 3D model generation, model evaluation, and model refinement phases, in order to acquire an efficient 3D model. Intensity gradients and incremental Delaunay triangulation are used in the Initial model generation. In this phase, a morphological edge operator is adopted for a fast edge filtering, and the incremental Delaunay triangulation is modified to decrease the computation time by avoiding the calculation errors of whole pixels and selecting a vertex at the near of the centroid within the previous triangle. After the model generation, sparse vertices are matched, then the faces are evaluated with the size, approximation error, and disparity fluctuation of the face in evaluation stage. Thereafter, the faces which have a large error are selectively refined into smaller faces. Experimental results showed that the proposed algorithm could acquire an adaptive model with less modeling errors for both smooth and abrupt areas and could remarkably reduce the model acquisition time.