• Korean journal of communication and information
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• v.48
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• pp.90-108
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• 2009

While the term of the institution as social manifestation has been discussed intensively through various theoretical approaches over the last few years in Social Sciences, such a debate has been missing so far in Communication Sciences. This paper attempts a theoretical discussion about the media as an institution in the field of Communication Sciences by applying the theory of organizational sociological neo-institutionalism. This research started out with the question which influence exerts the media on organizations and participants. The media is understood as an institution in the sense of permanent monitoring systems which create a) normative expectations b) which become stronger in order to assert such normative expectations c) the norms are applied by the participants d) in this application process, the participants accept the organizations, look primarily for the chosen paragraphs and exert an influence to change the norms. Organizations orient themselves at the institutional rules, because this way, they want to gain legitimacy and support. The media unfold their influence on organizations through certain obligations in addition to the pressure of the participants who deal with the organization and the media. Thus, media cannot exert influence independent from the organizationbut the participants accept the situation, which is generated by the many conflicting processes within the organization, they analyse them and transfer them.

• Journal of the Korean Institute of Landscape Architecture
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• v.41 no.2
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• pp.1-10
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• 2013

This paper aims to make an aesthetic inquiry into representing modes of wilderness in western films. The western film was the first genre in earnest about natural landscape, covering vast areas of America from the East to the West. It adopted representative modes suited to physical characteristics of landscapes which produced aesthetic characteristics. In western films, wilderness was represented at a distance from the camera lens as a setting and an object of contemplation. In eastern forest landscapes, western films adopted the visual model of Hudson River School's landscape painting which expressed the transcendental sublime. The western semiarid region reproduced the warrior's gaze shot from a high angle, and, in this visual mode, wilderness was expressed as a demonic landscape derived from Burke's definition of the sublime. On one hand, the western desert was represented as a place of hardship shot at a low angle which expressed the vastness, unevenness and limitlessness of the desert owing to the absence of horizon. On the other hand, the mesas of Monument Valley have sublime characteristics of size and time. In western films, they play the role of an emblem by rising from the limitless desert on the horizon. The prospect-refuge relationship, the desire to see without being seen, is discovered in the representative mode of wilderness in western films. In this context, this study hopes to discover the archetype of landscape representation.

• Journal of Navigation and Port Research
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• v.39 no.1
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• pp.15-21
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• 2015

In high precision positioning systems based on GNSS, ambiguity resolution is an important procedure. Correct ambiguity leads to positioning results which have high precision between millimeters and centimeters. However, when the ambiguity is determined incorrectly, ensuring accuracy and precision of the positioning result is impossible. An ambiguity validation test is required to obtain correct ambiguity when ambiguity resolution is performed based on the ILS (Integer Least Squares), which shows the best performance in point of theory and experiment when compared with other methods such as IR (Integer Rounding) and IB (Integer Bootstrapping). Comparison between the candidates of the validation test is needed to judge ambiguity correctly, because ILS searches for candidates of integer ambiguity, unlike other methods which calculate only one integer ambiguity. We analyzed the experimental performance of ambiguity validation tests. R-ratio, F-ratio and W-ratio were adopted for analysis. The performance of validation tests was evaluated by classifying normal operation, detection, missed detection and false alarm. As a result, strengths and weaknesses of validation tests was showed to experimental. we concluded that validation tests must be selected according to environment.

• Korean Journal of Construction Engineering and Management
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• v.5 no.3 s.19
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• pp.79-87
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• 2004

Building industry clients are suggested to clarify requirements and needs properly at the pre-project stage. According to these they can develop options to meet their needs with considering their resources and business case. At this stage, they make decisions while professionals in the industry are not involving. This process is called client briefing at the pre-project stage. However, client briefing is not a discrete process only conducted at this stage; various clients briefings should be performed over a project lift cycle. The client briefing at the pre-project stage is more important than others as the value for the clients is clarified at this stage - they may not be satisfied for the project results even when the project is finished on time within budget if the value itself is incorrectly defined. Given that the client briefing is important as stated, this paper aims to review theory on client briefing focusing those at the pre-project stage. As a part of research, a prototype workshop for client briefing is held and findings from it are summarized. Finally, suggestions for conducting client briefing in Korea are presented in terms of directions of relevant research, systems in the industry and points that clients or client briefing consultants should consider.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.268-278
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• 2005

We consider constructing the generalized suffix way of strings A and B when the suffix arrays of A and B are given, j.e., merging two suffix arrays of A and B. There are efficient algorithms to merge some special suffix arrays such as the odd array and the even array. However, for the general case that A and B are arbitrary strings, no efficient merging algorithms have been developed. Thus, one had to construct the generalized suffix arrays of A and B by constructing the suffix array of A$\#$B$\$$ from scratch, even though the suffix ways of A and B are given. In this paper, we Present efficient merging algorithms for the suffix arrays of two arbitrary strings A and B drawn from constant and integer alphabets. The experimental results show that merging two suffix ways of A and B are about 5 times faster than constructing the suffix way of A$\#$B$\$$ from scratch for constant alphabets. Our algorithms include searching all suffixes of string B in the suffix array of A. To do this, we use suffix links in suffix ways and we developed efficient algorithms for computing the suffix links. Efficient computation of suffix links is another contribution of this paper because it can be used to solve other problems occurred in bioinformatics that should search all suffixes of a given string in the suffix array of another string such as computing matching statistics, finding longest common substrings, and so on. The experimental results show that our methods for computing suffix links is about 3-4 times faster than the previous fastest methods.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.306-313
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• 2005

Conditional branch prediction is an important technique for improving processor performance. Branch mispredictions, however, waste a large number of cycles, inhibit out-of-order execution, and waste electric power on mis-speculated instructions. Hence, the branch predictor with higher accuracy is necessary for good processor performance. In global-history-based predictors like gshare and GAg, many mispredictions come from commit update of the history. Some works on this subject have discussed the need for speculative update of the history and recovery mechanisms for branch mispredictions. In this paper, we present a simple mechanism for recovering the branch history after a misprediction. The proposed mechanism adds an age_counter to the original predictor and doubles the size of the branch history register. The age_counter counts the number of outstanding branches and uses it to recover the branch history register. Simulation results on the Simplescalar 3.0/PISA tool set and the SPECINTgS benchmarks show that gshare and GAg with the proposed recovery mechanism improved the average prediction accuracy by 2.14$\%$ and 9.21$\%$, respectively and the average IPC by 8.75$\%$ and 18.08$\%$, respectively over the original predictor.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.663-674
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• 2005

We propose a system aimed at achieving high energy-delay efficiency by using adaptive victim caches. Particularly, we investigate methods to improve the hit rates in the first level of memory hierarchy, which reduces the number of accesses to mort power consuming memory structures such as L2 cache. Victim cache is a memory element for reducing conflict misses in a direct-mapped L1 cache. We present two techniques to fill the victim cache with the blocks that have higher probability to be re-reqeusted by processor. Hit-based victim cache ks tilled with the blocks which were referenced frequently by processor. Replacement-based victim cache is filled with the blocks which were evicted from the sets where block replacements had happened frequently According to our simulations, replacement-based victim cache scheme outperforms the conventional victim cache scheme about $2\%$ on average and refutes the power consumption by up to $8\%$.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.9
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• pp.1177-1184
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• 1999

본 논문에서는 스캔플립프롭 선택 시간이 짧고 높은 고장 검출률(fault coverage)을 얻을 수 있는 새로운 부분스캔 설계 기술을 제안한다. 순차회로에서 테스트패턴 생성을 용이하게 하기 위하여 완전스캔 및 부분스캔 설계 기술이 널리 이용되고 있다. 스캔 설계로 인한 추가영역을 최소화 하고 최대의 고장 검출률을 목표로 하는 부분스캔 기술은 크게 구조분석과 테스트 가능도(testability)에 의한 설계 기술로 나누어 볼 수 있다. 구조분석에 의한 부분스캔은 짧은 시간에 스캔플립프롭을 선택할 수 있지만 고장 검출률은 낮다. 반면 테스트 가능도에 의한 부분스캔은 구조분석에 의한 부분스캔보다 스캔플립프롭의 선택 시간이 많이 걸리는 단점이 있지만 높은 고장 검출률을 나타낸다. 본 논문에서는 구조분석에 의한 부분스캔과 테스트 가능도에 의한 부분스캔 설계 기술의 장단점을 비교.분석하여 통합함으로써 스캔플립프롭 선택 시간을 단축하고 고장 검출률을 높일 수 있는 새로운 부분스캔 설계 기술을 제안한다. 실험결과 대부분의 ISCAS89 벤치마크 회로에서 스캔플립프롭 선택 시간은 현격히 감소하였고 비교적 높은 고장 검출률을 나타내었다.Abstract This paper provides a new partial scan design technique which not only reduces the time for selecting scan flip-flops but also improves fault coverage. To simplify the problem of the test pattern generation in the sequential circuits, full scan and partial scan design techniques have been widely adopted. The partial scan techniques which aim at minimizing the area overhead while maximizing the fault coverage, can be classified into the techniques based on structural analysis and testabilities. In case of the partial scan by structural analysis, it does not take much time to select scan flip-flops, but fault coverage is low. On the other hand, although the partial scan by testabilities generally results in high fault coverage, it requires more time to select scan flip-flops than the former method. In this paper, we analyzed and unified the strengths of the techniques by structural analysis and by testabilities. The new partial scan design technique not only reduces the time for selecting scan flip-flops but also improves fault coverage. Test results demonstrate the remarkable reduction of the time to select the scan flip-flops and high fault coverage in most ISCAS89 benchmark circuits.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.9
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• pp.1083-1095
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• 1999

최근 처리기와 입출력 시스템의 속도 차이가 점점 커짐에 따라 버퍼 캐쉬의 효율적인 관리가 더욱 중요해지고 있다. 버퍼 캐쉬는 블록 교체 정책과 선반입 정책에 의해 관리되며, 각 정책은 버퍼 캐쉬에서 블록의 가치 즉 어떤 블록이 더 가까운 미래에 참조될 것인가를 결정해야 한다. 블록의 가치는 응용들의 블록 참조 패턴의 특성에 기반하며, 블록 참조 패턴의 특성에 대한 정확한 분석은 올바른 결정을 가능하게 하여 버퍼 캐쉬의 효율을 높일 수 있다. 본 논문은 각 응용들의 블록 참조 패턴에 대한 특성을 분석하고 이를 자동으로 발견하는 기법을 제안한다. 제안된 기법은 블록의 속성과 미래 참조 거리간의 관계를 이용해 블록 참조 패턴을 발견한다. 이 기법은 2 단계 파이프라인 방법을 이용하여 온라인으로 참조 패턴을 발견할 수 있으며, 참조 패턴의 변화가 발생하면 이를 인식할 수 있다. 본 논문에서는 8개의 실제 응용 트레이스를 이용해 블록 참조 패턴의 발견을 실험하였으며, 제안된 기법이 각 응용의 블록 참조 패턴을 정확히 발견함을 확인하였다. 그리고 발견된 참조 패턴 정보를 블록 교체 정책에 적용해 보았으며, 실험 결과 기존의 대표적인 블록 교체 정책인 LRU에 비해 최대 57%까지 디스크 입출력 횟수를 줄일 수 있었다.Abstract As the speed gap between processors and disks continues to increase, the role of the buffer cache located in main memory is becoming increasingly important. The buffer cache is managed by block replacement policies and prefetching policies and each policy should decide the value of block, that is which block will be accessed in the near future. The value of block is based on the characteristics of block reference patterns of applications, hence accurate characterization of block reference patterns may improve the performance of the buffer cache. In this paper, we study the characteristics of block reference behavior of applications and propose a scheme that automatically detects the block reference patterns. The detection is made by associating block attributes of a block with the forward distance of the block. With the periodic detection using a two-stage pipeline technique, the scheme can make on-line detection of block reference patterns and monitor the changes of block reference patterns. We measured the detection capability of the proposed scheme using 8 real workload traces and found that the scheme accurately detects the block reference patterns of applications. Also, we apply the detected block reference patterns into the block replacement policy and show that replacement policies appropriate for the detected block reference patterns decreases the number of DISK I/Os by up to 57%, compared with the traditional LRU policy.