• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.591-594
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• 2001

In the W-CDMA system, cell search is one of the imporant functions of the mobile station searching for a cell and achieving spreading code and time synchronization to its downlink scrembling code. For the methods of cell search to optimize codes, three stages are considered: 1) slot synchronization, 2) frame synchronization, and 3) scrambling code identification. Channels for cell search are Primary Synchronization Channel (P-SCH), Secondary Synchronization Channel(S-SCH), and Common Pilot Channel (CPICH). In this paper, cell search is analyzed based on simulation. Rake receiver provides improvement of Performance as an increase of bandwidth because there are more available multipaths. In this paper, the performance of W-CDMA system employing RAKE receiver is evaluated by computer simulation over the types of ITU_R wideband channel model and spreading rate. The result shows that the performance of CDMA adapting RAKE receiver is improved by the increase of multipath components in equal level of the received power.

• Journal of Korea Multimedia Society
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• v.22 no.8
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• pp.887-896
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• 2019

In this paper, we discuss an optimization approach for time-synchronizations in networked simulators. This method is a sub-technology that is required to combine heterogeneous simulators into a single simulation. In previous time-synchronization studies, they had built a network system among networked simulators. The network system collects network packets and adds time-stamps to the networked packets based on the time that occurs in events of simulation objects in the individual simulators. Then, it sorts them in chronological order. Finally, the network system applies time-synchronization to each simulator participating in interworking sequentially. However, the previous approaches have a limitation in that other participating simulators should wait for while processing an event in a simulator in a time stamp order. In this paper, we attempt to solve the problem by optimizing time-synchronizations in networked simulation environments. In order to prove the practicality of our approach, we have conducted an experiment. Finally, we discuss the contributions of this paper.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.10
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• pp.1-9
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• 1992

This paper presents an effective synchronization algorithm. It is different from the existing synchronization methods by inserting appropriate synchronization instructions between statements according to different kinds of data dependencies. The overhead caused by too many synchronization instructions in a loop can be a critical problem. Synchronization optimization is a method which discriminates and eliminates the redundant synchronization instructions in a loop. In this paper, a new synchronization optimization algorithm is developed, and performance analysis using simulation on the UNIX operating system is carried out.

• Journal of Information Processing Systems
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• v.15 no.4
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• pp.890-903
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• 2019

The single carrier frequency domain equalization (SC-FDE) technology is an important part of the broadband wireless access communication system, which can effectively combat the frequency selective fading in the wireless channel. In SC-FDE communication system, the accuracy of timing synchronization directly affects the performance of the SC-FDE system. In this paper, on the basis of Schmidl timing synchronization algorithm a timing synchronization algorithm suitable for FPGA (field programmable gate array) implementation is proposed. In the FPGA implementation of the timing synchronization algorithm, the sliding window accumulation, quantization processing and amplitude reduction techniques are adopted to reduce the complexity in the implementation of FPGA. The simulation results show that the algorithm can effectively realize the timing synchronization function under the condition of reducing computational complexity and hardware overhead.

• Journal of the Korean Institute of Intelligent Systems
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• v.16 no.1
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• pp.18-23
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• 2006

The complex system synchronization methods improve based on synchronization theory; however, due to deeper level of complexity within complex system compared to that of chaos system, it is difficult to synchronize complex signals from complex system. In this paper, we proposed coupled-synchronization theory in the n-double scroll circuit and new embedding driven-synchronization theory, a method of accomplishing synchronization with only one parameter out of may parameters, in hyper-chaos circuit to apply synchronization in the complex system. By applying proposed synchronization method using computer simulation, we confirmed the accomplishment of superior synchronization in complex system.

• Journal of applied mathematics & informatics
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• v.35 no.3_4
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• pp.387-397
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• 2017

In order to react the dynamic behavior of the system more actually, it is necessary to solve the first problem of synchronization for Markovian jump complex network system in practical engineering problem. In this paper, the problem of local stochastic synchronization for Markovian nonlinear coupled neural network system is investigated, including nonlinear coupling terms and mode-dependent delays, that is less restriction to other system. By designing the Lyapunov-Krasovskii functional and applying less conservative inequality, we get a new criterion to ensure local synchronization in mean square for Markovian nonlinear coupled neural network system. The criterion introduced some free matrix variables, which are less conservative. The simulation confirmed the validity of the conclusion.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.3
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• pp.235-241
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• 2020

In this paper, we propose the bus/bypass synchronization phase lock loop (B-Sync PLL) method using each phase voltage controller of a parallel UPS inverter. The B-Sync PLL included in each phase voltage control system of parallel UPS inverters has the transient response and the phase synchronization error at grid normal or blackout. The validity of this method is verified by simulation and experiment. As a result, the parallel UPS inverters using the proposed method confirmed that the output phase was continuously synchronized when a grid blackout, improving the transient response characteristics for stable load power supply and equal load sharing.

• Journal of the Korea Institute of Military Science and Technology
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• v.16 no.6
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• pp.819-827
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• 2013

Compared to legacy frequency hopping communications, future radio communications are required the secure and high data rate, ad-hoc network communication. In this paper, we have designed the network communication structure on the frequency hopping mode, and analyzed the performance of synchronization on the frequency hopping network radio systems. The design results are shown the initial sync. phase of approximately 9 hops and the traffic packet phase of approximately 30 hops. Also, we have simulated the performance on the communication conditions which are carrier bandwidth of 50kHz, user data rate of 64kbps and OQPSK modulation scheme in AWGN. In the simulation, we analyzed the correlation and the performance of synchronization success. The result of simulation show 99% probability for synchronization success at $E_b/N_o$ -4dB.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.199-200
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• 2008

In this paper, efficient time synchronization scheme for OFDM based WLAN system and its performance simulation results are presented. Assuming AGC and packet detection is done within 7 short training symbols. This scheme consists of coarse and fine estimation, and exhibits robustness over fading and AWGN channel. The presented synchronization scheme achieves the success rate of about 96% over the SNR of 5 dB.

• Journal of Advanced Navigation Technology
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• v.24 no.4
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• pp.285-290
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• 2020

This paper presents a time synchronization algorithm based on PLL for application to telemetry systems and implement FPGA logic. The large aircraft of the telemetry system acquires status information through each distributed acquisition devices and analyzes the flight status in real time. For this reason, time synchronization between systems is important to improve precision. This paper presents a PLL based time synchronization algorithm that is less complex than other time synchronization methods and takes less time to process data because there is minimized message transmission for synchronization. The validity of proposed algorithm is proved by simulation of Python. And the VHDL logic was implemented in FPGA to check the time synchronization performance.