• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.338-343
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• 2006

This paper describes about the design concept and the architecture of an economic VPN system which can perform fast crypto operations with cheap cost. The essence of the proposed system architecture is consisting of the system with two companion chips dedicated to VPN: one chip is a multi-purpose network processor for security machine and the other is a crypto acceleration chip which encrypt and decrypt network packets in a high speed. This study also addresses about some realizations that is required for fast prototyping such as the porting of an operating system, the establishment of compiler tool chain, the implementation of device drivers and the design of IPSec security engine. Especially, the second chip supports the most time consuming block cipher algorithms including 3DES, AES, and SEED and its performance was evaluated.

• Journal of Korea Multimedia Society
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• v.18 no.2
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• pp.244-252
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• 2015

This paper describes the design and implementation of a System-on-a-Chip (SoC) for face recognition to use in wearable/mobile products. The design flow starts from the system specification to implementation process on silicon. The entire process is carried out using a FPGA-based prototyping platform environment for design and verification of the target SoC. To ensure that the implemented face recognition SoC satisfies the required performances metrics, time analysis and recognition tests were performed. The motivation behind the work is a single chip implementation of face recognition system for target applications.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.161-172
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• 1994

This paper describes the design of a neurochip with on-chip learning capability in hardware with multiple processing elements. A digital architecture is adopted because its flexiblity and accuracy is advantageous for simulating the various application systems. The proposed chip consists of several processing elements to fit the large computation of neural networks, and has on-chip learning capability based on error back-propagation algorithm. It also minimizes the number of blobal control signals for processing elements. The modularity of the system makes it possible to buil various kinds of boards to match the expected range of applications.

• Journal of IKEEE
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• v.23 no.4
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• pp.1203-1207
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• 2019

As the number of IP cores has been increasing in a System-on-Chip (SoC), multiple routers are included in on-chip-networks. Each router has its own arbitration policy and it is difficult to obtain a desired arbitration result by combining multiple routers. Allocating desired bandwidths to the ports across the routers is more difficult. In this paper, a guaranteed bandwidth allocation scheme using an IP-level QoS control is proposed to overcome the limitations of existing local arbitration policies. Each IP can control the priority of a packet depending on the data communication requirement within the allocated bandwidth. The experimental results show that the proposed mechanism guarantees for IPs to utilize the allocated bandwidth in multiple router on-chip-networks. The maximum error rate of bandwidth allocation of the proposed scheme is only 1.9%.

• Biotechnology and Bioprocess Engineering:BBE
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• v.11 no.2
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• pp.146-153
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• 2006

A passive microfluidic delivery system using hydrophobic valving and pneumatic control was devised for microfluidic handling on a chip. The microfluidic metering, cutting, transport, and merging of two liquids on the chip were correctly performed. The error range of the accuracy of microfluid metering was below 4% on a 20 nL scale, which showed that microfluid was easily manipulated with the desired volume on a chip. For a study of the feasibility of biochemical reactions on the chip, a single enzymatic reaction, such as ${\beta}-galactosidase$ reaction, was performed. The detection limit of the substrate, i.e. fluorescein $di-{\beta}-galactopyranoside$ (FDG) of the ${\beta}-galactosidase$ (6.7 fM), was about 76 pM. Additionally, multiple biochemical reactions such as in vitro protein synthesis of enhanced green fluorescence protein (EGFP) were successfully demonstrated at the nanoliter scale, which suggests that our microfluidic chip can be applied not only to miniaturization of various biochemical reactions, but also to development of the microfluidic biochemical reaction system requiring a precise nano-scale control.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.5 s.182
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• pp.155-161
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• 2006

This paper introduces a new type of mechanical tape feeder for chip mounter. The mechanical feeder is composed of a pneumatic linear actuator and a linear feeding module with the application of a cam-slider. As semiconductor chips are getting smaller, PCB assembly makers require the feeder to position the chip with high accuracy. The linear feeding system improves the positioning accuracy of the chip by getting rid of the index error, which brings into existence on the sprocket rotating feeder. It also can make greatly reduce the dumping rate. The dumping error is caused by the impact occurred as the pawl to interrupt ratchet wheel rotation. The paper discusses its mechanism and mechanical performance. The positioning accuracy and the dynamic characteristic were measured for long time operation and analyzed. As a result, the feeder showed very good performance. However, the feeding system was dynamically unstable due to the cover film eliminator that is required to be modified

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8C
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• pp.806-813
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• 2009

This paper presents a modem chip design for high-speed wireless communications. Among the high-speed communication technologies, we design the UWB (Ultra-Wideband) modem SoC (System-on-Chip) Chip based on a MB-OFDM scheme which uses wide frequency band and gives low frequency interference to other communication services. The baseband system of the modem SoC chip is designed according to the standard document published by WiMedia. The SoC chip consists of FFT/IFFT (Fast Fourier Transform/Inverse Fast Fourier Transform), transmitter, receiver, symbol synchronizer, frequency offset estimator, Viterbi decoder, and other receiving parts. The chip is designed using 90nm CMOS (Complementary Metal-Oxide-Semiconductor) procedure. The chip size is about 5mm x 5mm and was fab-out in July 20th, 2009.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.93-100
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• 2003

The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.

• ETRI Journal
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• v.38 no.6
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• pp.1240-1249
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• 2016

With the number of IP cores in a multicore system-on-chip increasing to up to tens or hundreds, the role of on-chip interconnection networks is vital. We propose a networks-on-chip-style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade-off for the time saving, the time cost (TC) of the searched architecture is increased to up to 4.7% and 11.2%, respectively, at each step compared with that of the architecture obtained through full-case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to 13.1% when compared with that obtained through full-case exploration.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.65-72
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• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.