• 전자공학회지
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• 제29권3호
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• pp.41-48
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• 2002

This paper presents a basic concept of lab-on-a-chip systems and their advantages in chemical and biological analyses. In addition, magnetic bead-based immunoassay on a microfluidic system is also presented as a typical example of lab-on-chip systems. Rapid and low volume immunoassays have been successfully achieved on the demonstrated lab-on-a-chip using magnetic beads, which are used as both immobilization surfaces and bio-molecule carriers. Total time required for an immunoassay was less than 20 minutes including sample incubation time, and sample volume wasted was less than $50{\mu}l$ during five repeated assays. Lab-on-a-chip is becoming a revolutionary tool for many different applications in chemical and biological analysis due to its fascinating advantages (fast and low cost) over conventional chemical or biological laboratories. Furthermore, simplicity of lab-on-a-chip systems will enable self-testing capability for patients or health consumers overcoming space limitation.

• Journal of Information Processing Systems
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• 제2권3호
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• pp.189-193
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• 2006

In this study we propose an automatic reading system for diagnostic DNA chips. We define a general specification for an automatic reading system and propose a possible implementation method. The proposed system performs the whole reading process automatically without any user intervention, covering image acquisition, image analysis, and report generation. We applied the system for the automatic report generation of a commercialized DNA chip for cervical cancer detection. The fluorescence image of the hybridization result was acquired with a $GenePix^{TM}$ scanner using its library running in HTML pages. The processing of the acquired image and the report generation were executed by a component object module programmed with Microsoft Visual C++ 6.0. To generate the report document, we made an HWP 2002 document template with marker strings that were supposed to be searched and replaced with the corresponding information such as patient information and diagnosis results. The proposed system generates the report document by reading the template and changing the marker strings with the resultant contents. The system is expected to facilitate the usage of a diagnostic DNA chip for mass screening by the automation of a conventional manual reading process, shortening its processing time, and quantifying the reading criteria.

• 한국전자파학회논문지
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• 제20권12호
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• pp.1264-1271
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• 2009

본 논문에서는 이동 무선 통신 기기에 적합하고 다중 대역에서 동작하도록 설계된 칩 슬롯 안테나를 제안하였다. 제안된 안테나는 시스템 회로 기판(30 mm$\times$60 mm$\times$0.8 mm) 위에 칩 안테나(10 mm$\times$20 mm$\times$1.27 mm)를 접속시킨 구조이며, 안테나의 F자 형태의 패턴의 끝단은 비아를 통해 시스템 회로 기판과 연결되어졌다. 따라서 칩 안테나는 시스템 회로 기판의 마이크로스트립 선로로부터 접지면 슬롯 사이의 전이(transition)를 통하여 효과적으로 에너지를 방사한다. 제작된 안테나의 측정 결과 3:1 VSWR 임피던스 대역폭($\leq$-6 dB)은 1.98 GHz(1.61~3.59 GHz)와 0.8 GHz(5.2~6 GHz)로 나타났다. 제안된 안테나는 DCS, PCS, UMTS, WLAN의 주파수 대역을 만족함으로 무선 통신 기기에 적용 가능할 것으로 사료된다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 F
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• pp.2758-2760
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• 1999

ASIC chip design for motor control has been a subject of increasing interest since effective system-on-a-chip design methodology was developed. This paper investigates the design and implementation of ASIC chip for speed control of induction motor using VHDL which is a standarded hardware description language. The presented system is implemented using a simple electronic circuit based on FPGA.

• 한국정밀공학회지
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• 제20권5호
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.

• 한국정밀공학회지
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• 제15권2호
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• pp.99-106
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• 1998

In this paper, we have constructed an expert system for semiconductor chip encapsulation which combines a knowledge-based system with CAE software. The knowledge-base module includes heuristic and pre analysis knowledge for evaluation and redesign. Evaluation of the initial design and generation of redesign recommendations can be developed from the rules as applied to a given chip package. The CAE programs can be used for simulating the filling and packing stage of encapsulation process. The expert system is a new tool which enables package design or process conditions with high yields and high productivity.

• 유체기계공업학회:학술대회논문집
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• 유체기계공업학회 2006년 제4회 한국유체공학학술대회 논문집
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• pp.305-308
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• 2006

For controlling micro-flows inside a LOC (lab-on-a-chip) a syringe pump or an electronic device for EOF(electro-osmotic flow) have been used in general. However, these devices are so large and heavy that they are burdensome in the development of a portable micro-TAS (total analysis system). In this study, a new flow control system employing pressure chambers, digital switches and speed controllers was developed. This system could effectively control the micro-scale flows inside a LOC without any mechanical actuators or electronic devices We also checked the feasibility of this new control system by applying it to a LOC of micro-mixer type. Performance tests show that the developed control system has very good performance. Because the flow rate in LOC is controlled easily by throttling the speed controller, the flows in complicate microchannels network can be also controlled precisely.

• 한국기계가공학회지
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• 제12권6호
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• pp.175-181
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• 2013

The primary element of machining automation is to maximize the utilization of machine tools, which determines the output and lead-time. In particular, 95% of raw materials for wing ribs are cut into chips and 0.6 ton of chips are generated every hour from each machine tool. In order to verify the chip recycling system that controls the chips from the machines in five-axis FMS line, a simulation of the virtual model is constructed using the QUEST simulation program. The optimum speed of the chip conveyor and its operating conditions that directly affect the efficiency of the FMS line are presented including the chip conveyor speed, the maximum capacity of the hopper, and the number of chip compressors.

• Journal of information and communication convergence engineering
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• 제19권3호
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• pp.175-179
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• 2021

Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover, a hardware-based FI can cause permanent damage to the target system, because the actual circuit cannot be restored. Accordingly, we propose a simulation-based FI framework based on the Verilog Procedural Interface for measuring the failure rates of SoCs caused by soft errors. We execute five benchmark programs using an ARM Cortex M0 processor and inject soft errors using the proposed framework. The experiment has a 95% confidence level with a ±2.53% error, and confirms the reliability and feasibility of using proposed framework for fault analysis in SoCs.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 B
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• pp.1295-1297
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• 1996

CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.