• Journal of IKEEE
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• v.22 no.1
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• pp.104-109
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• 2018

This paper presents a hardware design for the block encryption algorithm of ARIA which is used for standard in Korea. It presents a hardware-efficient design to increase the throughput for the ARIA algorithm using a high-speed pipeline architecture. We have used ROM for the S-box implementation. This approach aims to decrease the critical path delay of the encryption. In this paper, hardware was designed by VHDL, realized RTL level by Synplify which is synthesis tool and verified simulation by ModelSim. The ARIA algorithm is shown 68.3 MHz (Maximum operation frequency) to use Xilinx VertxE XCV Series device.

• Journal of Powder Materials
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• v.20 no.4
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• pp.285-290
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• 2013

$Ti_2AlN$ composites are a laminated compounds that posses unique combination of typical ceramic properties and typical metallic(Ti alloy) properties. In this paper, the powder synthesis, SPS sintering, composite characteristics and machinability evaluation were systematically conducted. The random orientation characteristics and good crystallization of the $Ti_2AlN$ phase are observed. The electrical and thermal conductivity of $Ti_2AlN$ is higher than that of Ti6242 alloy. A machining test was carried out to compare the effect of material properties on micro electrical discharge drilling for $Ti_2AlN$ composite and Ti6242 alloy. Also, mixture table as a kind of tables of orthogonal arrays was used to know how parameter is main effective at experimental design. Consequently, hybrid $Ti_2AlN$ ceramic composites showed good machining time and electrode wear shape under micro ED-drilling process. This conclusion proves the feasibility in the industrial applications.

• Phonetics and Speech Sciences
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• v.7 no.1
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• pp.21-26
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• 2015

The aim of this study is to synthesize pathological breathy voice and to make a cepstral peak prominence (CPP) table following breathiness ranks by cepstral analysis to supplement reliability of the perceptual auditory judgment task. KlattGrid synthesizer included in Praat was used. Synthesis parameters consist of two groups, i.e., constants and variables. Constant parameters are pitch, amplitude, flutter, open phase, oral formant and bandwidth. Variable parameters are breathiness (BR), aspiration amplitude (AH), and spectral tilt (TL). Five hundred sixty samples of synthetic breathy vowel /a/ for male were created. Three raters participated in ranking of the breathiness. 217 were proved to be inadequate samples from perceptual judgment and cepstral analysis. Finally, 343 samples were selected. These CPP values and other related parameters from cepstral analysis are classified under four breathiness ranks (B0~B3). The mean and standard deviation of CPP is $16.10{\pm}1.15$ dB(B0), $13.68{\pm}1.34$ dB(B1), $10.97{\pm}1.41$ dB(B2), and $3.03{\pm}4.07$ dB(B3). The value of CPP decreases toward the severe group of breathiness because there is a lot of noise and a small quantity of harmonics.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.6
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• pp.51-57
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• 1980

Any switching function can be constructed with universal building block of MAND gate. Threelevel AND-NOT logic networks with only true inputs are called TANT networks. Systematic approach to TANT minimization starts from the UF type minterm with the smallest subscript and ends when UF type minterms are all covered. Optinal PEI is composed of CPPI or EPPi without C-C table. The algorithm in this work is usful in solving TANT optimization porblem of four or five variables by hand solution. When variable are six or more, it is required to be solved by computer, A CAD software package of this algorithm with FORTRAN IV language is made to solve such problems.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.30 no.1
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• pp.132-138
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• 2002

Of srategic importance nowdays is the development of high performance spacecraft bus. In this study, optimization for spacecraft structure is performed under the framework of coupled load analysis which is a branch of component mode synthesis with constrained mode and modal transient analysis. unlike the traditional method which uses the quasi-static table supplied by launch vehicle contractor, the present method adots the load results of previous coupled load analysis. It if shown that the proposed method can serve as a effective tool for the optimization spacecraft structure in the early stage of design and weight reduction by numerical example.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1482-1489
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• 1998

This paper aims to extract characteristics of the spectrum of fingerprint image and to apply them to image enhancement techniques in spatial frequency domain. Based on 1$\times$64 window as a processing unit and the different record lengths(32, 16, 8), the estimate of power spectrum density for each length was made. Each acquired spectrum characteristics was applied to the re-synthesis process of the fingerprint image, an improved gray scale image was obtained. In order to select an optimal predictor and the Huffman table for the fingerprint iamge, the lossless JPEG algorithm was used. Experiments were performed for extracting distribution characteristics for the each of 7 predictors from the fingerprint image and modeling processes, and the result was applied to the data compression algorithm and the selection of the optimal predictor.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.9
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• pp.536-542
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• 2004

An architecture of direct digital frequency synthesizers (DDFS) is studied in this paper The Direct digital frequency synthesizers (DDFS) provide fast frequency switching with high spectral purity and are widely used in modern spread spectrum wireless communication systems. ROM-based DDFS uses a ROM lookup table to store the amplitude of a sine wave. In this paper, we suggest three new techniques to reduce the ROM size. One new technique uses more number of hierarchical levels in ROM structures. Another techniques use simple interpolation techniques combined with hierarchical ROM structures. A 12 bit sine wave is generated by using these techniques. Experimental results show that the new proposed techniques can reduce the required ROM size by up to 24%, when compared to that of a resent method[1].

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.512-522
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• 2003

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Typically, the size of the chip required to implement the circuit depends on both the maximum number of the LUT blocks required to implement the function of each subcircuit and the maximum number of micro-registers to store results over context switches in the same time. Therefore, many partitioning or synthesis methods try to minimize these two factors. In this paper, we present a new estimation technique to find the lower bound on the number of micro-registers which can be obtained by any synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. If the estimated lower bound exactly matches the actual number in the actual design result, we can say that the result is guaranteed to be optimal. In contrast, if they do not match, the following two cases are expected: we might estimate a better (more exact) lower bound or we find a new synthesis result better than those of the previous work. Our experimental results show that there are some differences between the numbers of micro-registers and our estimated lower bounds. One reason for these differences seems that our estimation tries to estimate the result with the minimum micro-registers among all the possible candidates, regardless of usage of other resources such as LUTs, while the previous work takes into account both LUTs and micro-registers. In addition, it implies that our method may have some limitation on exact estimation due to the complexity of the problem itself in sense that it is much more complicated than LUT estimation and thus needs more improvement, and/or there may exist some other synthesis results better than those of the previous work.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.37-47
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• 2016

The practical constraints on the commercial FPGAs which contain dedicated wide function multiplexers in their slice structure are incorporated with one of the most advanced FPGA mapping algorithms based on the AIG (And-Inverter Graph), one of the best logic representations in academia. As the first step of the mapping process, cuts are enumerated as intermediate structures. And then, the cuts which can be mapped to the multiplexers are recognized. Without any increased complexity, the delay and area of multiplexers as well as LUTs are calculated after checking the requirements for the tree construction such as symmetry and depth limit against dynamically changing mapping of neighboring nodes. Besides, the root positions of multiplexer trees are identified from the RTL code, and annotated to the AIG as AOs (Auxiliary Outputs). A new AIG embedding the multiplexer tree structures which are intentionally synthesized by Shannon expansion at the AOs, is overlapped with the optimized AIG. The lossless synthesis technique which employs FRAIG (Functionally Reduced AIG) is applied to this approach. The proposed approach and techniques are validated by implementing and applying them to two RISC processor examples, which yielded 13~30% area reduction, and up to 32% delay reduction. The research will be extended to take into account the constraints on the dedicated hardware for carry chains.

• The Journal of the Korea Contents Association
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• v.12 no.10
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• pp.116-127
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• 2012

With the recent rapid growth in the number of people who enjoy marine and leisure activities in Korea, the marine leisure industry faces good opportunities for development. Korean brands are in between them. In this situation, new and innovative products related to an inflatable tube, which is one of the most popular marine leisure items, will help to increase sales of domestic companies and to pioneer a new market. Research methods are largely divided into 4: investigation, analysis & synthesis, development and evaluation. This paper introduces a "tube cushion" which is an inflatable tube covered by fabrics. It can be functioned at home 365 days a year as a cushion or a children's plaything. Tactile fabrics, neoprene and air-mesh, are used as the cover with a zipper, making it easy to open and close. Moreover, by putting together tubes and connecting them with snap fastener attached straps, the cushion can be transformed into a chair, a table, a tunnel, a train, and so on, serving as a creative plaything for children. With this paper, it is expected that new and innovative items differentiated from others, like this crossover tube cushion, will help to create a 'Blue Ocean' market for the marine leisure industry from the long-term perspective.