• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.532-540
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• 2014

It is necessary to measure the current of rotor for controlling the active and reactive power generated by the stator side of the doubly fed induction generator (DFIG) system. There are offset and scaling errors in the current measurement. The offset and scaling errors cause one and two times current ripples of slip frequency in the synchronous reference frame of vector control, respectively. This paper proposes a compensation method to reduce their ripples. The stator current is variable according to the wind force but the rotor current is almost constant. Therefore input of the rotor current is more useful for a compensation method. The proposed method adopts the synchronous d-axis current of the rotor as the input signal for compensation. The ripples of the measurement errors can be calculated by integrating the synchronous d-axis stator current. The calculated errors are added to the reference current of rotor as input of the current regulator, then the ripples are reduced. Experimental results show the effectiveness of the proposed method.

• Journal of Power Electronics
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• 제17권2호
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• pp.533-541
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• 2017

This paper presents a novel Parameter-Independent Fictive-Axis (PIFA) approach for the Voltage-Oriented Control (VOC) algorithm used in grid-tied single-phase inverters. VOC is based on the transformation of the single-phase grid current into the synchronous reference frame. As a result, an orthogonal current signal is needed. Traditionally, this signal has been obtained from fixed time delays, digital filters or a Hilbert transformation. Nevertheless, these solutions present stability and transient drawbacks. Recently, the Fictive Axis Emulation (FAE) VOC has emerged as an alternative for the generation of the quadrature current signal. FAE requires detailed information of the grid current filter along with its transfer function for signal creation. When the transfer function is not accurate, the direct and quadrature current components present steady-state oscillations as the fictive two-phase system becomes unbalanced. Moreover, the digital implementation of the transfer function imposes an additional computing burden on the VOC. The PIFA VOC presented in this paper, takes advantage of the reference current to create the required orthogonal current, which effectively eliminates the need for the filter transfer function. Moreover, the fictive signal amplitude and phase do not change with a frequency drift, which results in an increased reliability. This yields a fast, linear and stable system that can be installed without fine tuning. To demonstrate the good performance of the PIFA VOC, simulation and experimental results are presented.

• 전력전자학회논문지
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• 제15권2호
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• pp.142-149
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• 2010

매입형 영구자석 동기 전동기는 높은 효율과 빠른 동특성, 넓은 정출력 운전 영역 등의 장점 때문에 다양한 산업 분야에서 각광을 받고 있다. 특히 매입형 영구자석 동기기의 단위 전류당 최대 토크(Maximum Torque Per Ampere, MTPA) 운전 방법은 전동기의 최대 효율 운전을 위해서 필수적인 운전방법이 되었다. 이론적인 MTPA 운전점은 전동기의 제 정수에 의해 결정되는데, 매입형 영구자석 동기 전동기는 온도와 운전 영역에 따라 전동기 제 정수의 변화가 심하여 정확한 MTPA 운전을 하기 위해서는 전동기의 전 운전 영역에 대한 전동기 제 정수를 미리 알고 있어야 한다. 본 논문에서는 신호 주입 개념을 도입한 새로운 MTPA 운전 방법을 제안한다. 전류에 높은 주파수의 신호를 주입하여 그 주입된 신호에 의한 반응을 확인함으로 MTPA 운전점을 판별하게 된다. 이 방법은 전동기 제 정수 변동에 강인하며, 간단한 신호처리 과정을 통하여 MTPA 운전을 할 수 있다.

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2000년도 하계종합학술대회논문집
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• pp.61-64
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• 2000

본 논문에서는 cdma2000 규격을 채용한 역방향 링크 동기식 DS-CDMA 시스템을 시뮬레이션 하여 시스템의 성능을 분석하려다 cdma2000 시스템은 기존의 IS-95와는 달리 Pilot 채널을 이용하여 페이딩 채널을 추정하고 이를 이용하여 채널 환경에 의한 수신신호의 위상변화를 보상해 준다. 채널 추정필이 31pcg 심볼에서 Pilot 채널과 Traffic 채널의 최적의 전력비를 구하였다. 또한 시스템에 Power Control을 적용하여 Target FER을 만족시키기 위한 required Eb/No를 구하였고, 서로 다른 데이터율의 사용자가 동시에 전송할 때의 성능을 분석하였다.

• 반도체디스플레이기술학회지
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• 제10권4호
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• pp.7-13
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• 반도체디스플레이기술학회지
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• 제10권3호
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• pp.1-6
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 기술교육위원회 창립총회 및 학술대회 의료기기전시회
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• pp.34-37
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• 2001

This research suggested the new algorithm controlled by micro processor which is already stored by various PWM form of output voltage by using fundamental data of the carrier and signal. The determined PWM pattern is not concerned with the signal wave form and the new algorithm can obtain the desired pulse width by synchronous of carrier. The PWM wave can be controlled with real time by using extra hardware and digital software and to speed up program processing, the control signals to switch the power semi-conductor of three phase PWM inverter, simultaneously use the output signal by microprocessor and extra hardware, and control signal by software. In the end, this method was proved by applying to Three phase voltage source inverter.

• 음성과학
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• 제7권3호
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• pp.153-165
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• 2000

During the phonation of voiced sounds, instants exist where the glottis is opened or closed, due to the periodic vibration of the vocal cord. When closed, this is called the glottal closure instant(GCI) or epoch.. The correct detection of the GCI is one of the important problems in speech processing for pitch detection, pitch synchronous analysis, and so on. Recently, it has been shown that the local maxima points of the wavelet transformed speech signal correspond to the GCIs of speech signal. In this paper, we investigate the accuracy of Gels estimated from this wavelet transformed speech signal. For this purpose we compare them with the negative peak points of the differentiated EGG signal that represents the actual GCIs of speech signal.

• Journal of Electrical Engineering and Technology
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• 제13권4호
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• pp.1558-1565
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• 2018

Three-phase current is reconstructed from the dc-link current in an AC machine drive with a single current sensor. Switching pattern modification methods, in which the magnitude of the effective voltage vector is secured over its minimum, are investigated to accurately reconstruct the three-phase current. However, the existing methods that modify the switching pattern cause voltage and current distortions that degrade sensorless performance. This paper proposes a variable-magnitude voltage signal injection method based on a high frequency voltage signal injection. The proposed method generates a voltage reference vector that ensures the minimum magnitude of the effective voltage vector by varying the magnitude of the injection signal. This method can realize high quality current reconstruction without switching pattern modification. The proposed method is verified by experiments in a 600W Interior permanent magnet synchronous machine (IPMSM) drive system.

• Journal of Power Electronics
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• 제16권4호
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• pp.1513-1525
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• 2016

Rapid and accurate phase synchronization is critical for the reliable control of grid-tied inverters. However, the commonly used software phase-locked loop methods do not always satisfy the need for high-speed and accurate phase synchronization under severe grid imbalance conditions. To address this problem, this study develops a novel open-loop phase locking scheme based on a synchronous reference frame. The proposed scheme is characterized by remarkable response speed, high accuracy, and easy implementation. It comprises three functional cascaded blocks: fast orthogonal signal generation block, fast fundamental-frequency positive sequence component construction block, and fast phase calculation block. The developed virtual orthogonal signal generation method in the first block, which is characterized by noise immunity and high accuracy, can effectively avoid approximation errors and noise amplification in a wide range of sampling frequencies. In the second block, which is the foundation for achieving fast phase synchronization within 3 ms, the fundamental-frequency positive sequence components of unsymmetrical grid voltages can be achieved with the developed orthogonal signal construction strategy and the symmetrical component method. The real-time grid phase can be consequently obtained in the third block, which is free from self-tuning closed-loop control and thus improves the dynamic performance of the proposed scheme. The proposed scheme is adaptive to severe unsymmetrical grid voltages with sudden changes in magnitude, phase, and/or frequency. Moreover, this scheme is able to eliminate phase errors induced by harmonics and random noise. The validity and utility of the proposed scheme are verified by the experimental results.