• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 A
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• pp.49-51
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• 1999

The direct thrust control of permanent magnet linear synchronous motor using digital signal processor (DSP) is presented. The motor self inductance, the initial flux linkage by the permanent magnet is calculated in advance by the finite element analysis. The equivalent circuit method and the digital signal processor are used for the simulation and experiment, respectively. The simulation and experimental results such as, thrust, current and speed responses to the commands are examined.

• Journal of Power Electronics
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• 제9권4호
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• pp.582-592
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• 2009

This paper proposes a new speed sensorless direct torque and flux controlled interior permanent magnet synchronous motor (IPMSM) drive. Closed-loop control of both the torque and stator flux linkage are achieved by using two proportional-integral (PI) controllers. The reference voltage vectors are generated by a SVM unit. The drive uses an adaptive sliding mode observer for joint stator flux and rotor speed estimation. Global asymptotic stability of the observer is achieved via Lyapunov analysis. At low speeds, the observer is combined with the high frequency signal injection technique for stable operation down to standstill. Hence, the sensorless drive is capable of exhibiting high dynamic and steady-state performances over a wide speed range. The operating range of the direct torque and flux controlled (DTFC) drive is extended into the high speed region by incorporating field weakening. Experimental results confirm the effectiveness of the proposed method.

• Journal of Electrical Engineering and Technology
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• 제9권5호
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• pp.1582-1591
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• 2014

This paper presents a hybrid sensorless control for an interior permanent magnet synchronous motor (IPMSM) for zero-, low-, and high-speed regions. Many sensorless control methods such as an observer-based estimator have been introduced. However, most of the observer-based estimators have a disadvantage at start-up and in the low-speed region. To solve this problem, a simple strategy of using a hybrid system is proposed by integrating a high-frequency (HF) signal injection method and a full-order flux observer. In addition, an HF signal injection method with only a low pass filter (LPF) is proposed to simplify the hybrid system. The hybrid system achieves high-performance drive throughout the entire speed range. The effectiveness of the proposed hybrid technique is verified by experiments using an 11-kW IPMSM drive system.

• 한국정보통신학회논문지
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• 제20권3호
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• pp.577-582
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• 2016

전류 컨베이어를 사용하는 카운터 타입의 동기형 시간-디지털 변환기를 공급전압 3volts에서 $0.18{\mu}m$ CMOS 공정을 이용하여 설계하였다. 비동기 시간-디지털 변환기의 단점을 보완하기 위해 클록은 시작신호가 인가되면 시작신호와 동기화되어 생성된다. 비동기형 시간-디지털 변환기에서 디지털 출력 값의 에러는 클록주기인 $-T_{CK}$에서 $T_{CK}$이다. 그러나 동기형 시간-디지털 변환기의 경우 에러는 0에서 $T_{CK}$이다. 시작신호와 클록의 동기화로 인하여 시간간격 신호를 디지털 값으로 변환할 때 출력 값의 에러 범위는 감소한다. 또한 고주파의 외부 클럭을 사용하지 않음에 따라 회로의 구성이 간단하다. 설계된 시간-디지털 변환기의 동작은 HSPICE 시뮬레이션을 통하여 확인하였다.

• 한국정보과학회논문지:시스템및이론
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• 제26권8호
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• pp.918-929
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• 1999

동기식 스트림 암호통신 방식을 사용하는 암호통신에서는 암/복호화 과정 수행시 암호통신 과정에서 발생하는 사이클슬립으로 인해 키수열의 동기이탈 현상이 발생되고 이로 인해 오복호된 데이타를 얻게된다. 이러한 위험성을 감소하기 위한 방안으로 현재까지 암호문에 동기신호와 세션키를 주기적으로 삽입하여 동기를 이루는 주기적인 동기암호 통신방식을 사용하여 왔다. 본 논문에서는 CDMA(Cellular Division Multiple Access) 이동망에서 데이타서비스를 제공할 때 사용되는 점대점 프로토콜의 주소영역의 특성을 이용하여 단위 측정시간 동안 측정된 주소비트 정보와 플래그 패턴의 수신률을 이용하여 문턱 값보다 작은경우 동기신호와 세션키를 전송하는 비주기적인 동기방식을 사용하므로써 종래의 주기적인 동기방식으로 인한 전송효율성 저하와 주기적인 상이한 세션키 발생 및 다음 주기까지의 동기이탈 상태의 지속으로 인한 오류확산 등의 단점을 해결하였다. 제안된 알고리즘을 링크계층의 점대점 프로토콜(Point to Point Protocol)을 사용하는 CDMA 이동망에서 동기식 스트림 암호 통신방식에 적용시 동기이탈율 10-7의 환경에서 주기가 1sec인 주기적인 동기방식에서 요구되는 6.45x107비트에 비해 3.84x105비트가 소요됨으로써 전송율측면에서의 성능향상과 오복호율과 오복호 데이타 비트측면에서 성능향상을 얻었다. Abstract In the cipher system using the synchronous stream cipher system, encryption / decryption cause the synchronization loss (of key arrangement) by cycle slip, then it makes incorrect decrypted data. To lessen the risk, we have used a periodic synchronous cipher system which achieve synchronization at fixed timesteps by inserting synchronization signal and session key. In this paper, we solved the problem(fault) like the transfer efficiency drops by a periodic synchronous method, the periodic generations of different session key, and the incorrectness increases by continuing synchronization loss in next time step. They are achieved by the transfer of a non-periodic synchronous signal which carries synchronous signal and session key when it is less than the threshold value, analyzing the address field of point-to-point protocol, using the receiving rate of address bits information and flag patterns in the decision duration, in providing data services by CDMA mobile network. When the proposed algorithm is applied to the synchronous stream cipher system using point-to-point protocol, which is used data link level in CDMA mobile network, it has advanced the result in Rerror and Derror and in transmission rate, by the use of 3.84$\times$105bits, not 6.45$\times$107bits required in periodic synchronous method, having lsec time step, in slip rate 10-7.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2009년도 정기총회 및 추계학술대회 논문집
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• pp.93-95
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• 2009

The synchronous PI current controller has been widely used for the high performance PM synchronous drives and generally implemented using a digital signal processor. This paper describes the control characteristics of the digital PI current controller for PM synchronous drives. The stability of the current control system considering the sampling time is investigated and the effects of the mismatched decoupling terms in the discrete-time domain are also discussed. The simulation results are provided to verify the theoretic results.

• Journal of international Conference on Electrical Machines and Systems
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• 제1권2호
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• pp.58-63
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• 2012

The Test Signal Method is adopted to analyze the impact of thyristor controlled series capacitor (TCSC) on sub-synchronous oscillation. The results show that the simulation system takes the risk of Sub-synchronous Oscillation (SSO) while the TCSC is operating in the capacitive region. A supplementary excitation damping controller (SEDC) is used to mitigate SSO caused by the TCSC. A new optimization method which is aimed for optimal phase compensation is proposed. This method is realized by using the particle swarm optimization (PSO) algorithm. The simulation results show that the SEDC designed by this method has superior suitability, and that the secure operation scope of the TCSC is greatly increased.

• Journal of Power Electronics
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• 제2권1호
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• pp.55-66
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• 2002

A new on-line dead-time compensation method for a permanent magnet (PM) synchronous motor drive is proposed. Using a simple disturbance observer without any additional circuit and off-line experimental measurement, disturbance voltages in the synchronous reference dq frame caused by the dead time and non-ideal switching characteristics of power devices are estimated in an on-line manner and fed to voltage references in order to compensate the dead-time effects. The proposed method is applied to a PM synchronous motor drive system and implemented by using software of a digital signal processor (DSP) TMS320C31. Simulations and experiments are carried out for this system and the results well demonstrate the effectiveness of the proposed method.

• Journal of Power Electronics
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• 제9권5호
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• pp.757-771
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• 2009

This paper proposes a systematic approach to the modeling of the small-signal characteristics of three-phase bridge boost rectifiers under non-sinusoidal conditions. The main obstacle to the conventional synchronous d-q frame modeling approach is that it is unable to identify a steady-state under non-sinusoidal conditions. However, for most applications under non-sinusoidal conditions, the current loops of boost rectifiers are designed to have a bandwidth that is much higher than typical harmonics frequencies in order to achieve good current control for these harmonic components. Therefore a quasi-static method is applied to the proposed modeling approach. The converter small-signal characteristics developed from conventional synchronous frame modeling under different operating points are investigated and a worst case point is then located for the current loop design. Both qualitative and quantitative analyses are presented. It is observed that operating points influence the converter low frequency characteristics but hardly affect the dominant poles. The relationship between power stage parameters, system poles and zeroes is also presented which offers good support for the system design. Both the simulation and experimental results verified the analysis and proposed modeling approach. Finally, the practical case of a parallel active power filter is studied to present the modeling approach and the resultant regulator design procedure. The system performance further verifies the whole analysis.

• 전자공학회논문지A
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• 제30A권2호
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• pp.1-9
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• 1993

For frame synchronization in synchronous multiplexer based on SDH (Synchronous Digital Hierarchy), pointer justification mechanism (opinter adjustment) to compensate small frequency differences between the received uline clock and local clock is sed. But these pointer adjustment will introduce jitter onto tributary signal. This paper presents the bit leaking method to reduce those jitter to a level compatible with existing specification, where the simulation shows that this method reduces pointer adjustment jitter.