• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.6
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• pp.243-249
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• 2010

In this thesis, in order to a equivalent circuit-analytical study for a symmetric double gate type MOSFET, we slove analytically the 2D Poisson's equation in a a silicon body. To solve the threshold voltage in a symmetric double gate type MOSFET from the derived expression for the surface potential which the two-dimensional potential distribution of a symmetric double gate type MOSFET is assumed approximately. This thesis can use short and long channel in a silicon body we introduce a new the threshold voltage model in a symmetric double gate type MOSFET and measure it the distance about the range of channel length up to 0.1 [${\mu}m$].

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.2939-2945
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• 2014

This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend greatly differs with bottom gate voltage, channel length and thickness, and doping concentration.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.755-758
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• 2014

This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend very differs with bottom gate voltage, channel length and thickness, and doping concentration.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.342-354
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• 2013

The aim of this work is to investigate and study the quantum effects in the modeling of nanoscale symmetric double-gate InAlAs/InGaAs/InP HEMT (High Electron Mobility Transistor). In order to do so, the carrier concentration in InGaAs channel at gate lengths ($L_g$) 100 nm and 50 nm, are modelled by a density gradient model or quantum moments model. The simulated results obtained from the quantum moments model are compared with the available experimental results to show the accuracy and also with a semi-classical model to show the need for quantum modeling. Quantum modeling shows major variation in electron concentration profiles and affects the device characteristics. The two triangular quantum wells predicted by the semi-classical model seem to vanish in the quantum model as bulk inversion takes place. The quantum effects thus become essential to incorporate in nanoscale heterostructure device modeling.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.156-162
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• 2015

This paper has analyzed how conduction path and electron concentration for the device parameters such as oxide thickness, channel doping, and top and bottom gate voltage influence on subthreshold swing of asymmetric double gate MOSFET. Compared with symmetric and asymmetric double gate MOSFET, asymmetric double gate MOSFET has the advantage that the factors to be able to control the short channel effects increase since top and bottom gate oxide thickness and voltages can be set differently. Therefore the conduction path and electron concentration for top and bottom gate oxide thickness and voltages are investigated, and it is found the optimum conditions that the degradation of subthreshold swing, severe short channel effects, can reduce. To obtain the analytical subthreshold swing, the analytical potential distribution is derived from Possion's equation. As a result, conduction path and electron concentration are greatly changed for device parameters, and subthreshold swing is influenced by conduction path and electron concentration of top and bottom.

• Journal of Power Electronics
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• v.15 no.4
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• pp.951-963
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• 2015

In this paper, a new symmetric multilevel inverter is proposed. A simple structure for the cascaded multilevel inverter topology is also proposed, which produces a high number of levels with the application of few power electronic devices. The symmetric multilevel inverter can generate 2n+1 levels with a reduced number of power switches. The basic unit is composed of a single and double source unit (SDS-unit). The application of this SDS-unit is for reducing the number of power electronic components like insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocked voltages by switches. Various new algorithms are recommended to determine the magnitude of dc sources in a cascaded structure. Furthermore, the proposed topology is optimized for different goals. The proposed cascaded structure is compared with other similar topologies. For verifying the performance of the proposed basic symmetric and cascaded structure, results from a computer-based MATLAB/Simulink simulation and from experimental hardware are also discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.107-117
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• 2010

An analytical subthreshold swing model is presented for symmetric double-gate (DG) MOSFETs with Gaussian doping profile in vertical direction. The model is based on the effective conduction path effect (ECPE) concept of uniformly doped symmetric DG MOSFETs. The effect of channel doping on the subthreshold swing characteristics for non-uniformly doped device has been investigated. The model also includes the effect of various device parameters on the subthreshold swing characteristics of DG MOSFETs. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained by using the commercially available $ATLAS^{TM}$ device simulator. The model is believed to provide a better physical insight and understanding of DG MOSFET devices operating in the subthreshold regime.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.163-168
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• 2015

This paper analyzed the deviation of tunneling current for bottom gate voltage of sub-10 nm asymmetric double gate MOSFET. The asymmetric double gate MOSFET among multi gate MOSFET developed to reduce the short channel effects has the advantage to increase the facts to be able to control the channel current, compared with symmetric double gate MOSFET. The increase of off current is, however, inescapable if aymmetric double gate MOSFET has the channel length of sub-10 nm. The influence of tunneling current was investigated in this study as the portion of tunneling current for off current was calculated. The tunneling current was obtained by the WKB(Wentzel-Kramers-Brillouin) approximation and analytical potential distribution derived from Poisson equation. As a results, the tunneling current was greatly influenced by bottom gate voltage in sub-10 nm asymmetric double gate MOSFET. Especially it showed the great deviation for channel length, top and bottom gate oxide thickness, and channel thickness.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.331-341
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• 2013

In the present work, the effect of the gate-to-drain capacitance ($C_{gd}$) on the noise performance of a symmetric tied-gate $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}As$ double-gate HEMT is studied using an accurate charge control based approach. An analytical expression for the gate-to-drain capacitance is obtained. In terms of the intrinsic noise sources and the admittance parameters ($Y_{11}$ and $Y_{21}$ which are obtained incorporating the effect of $C_{gd}$), the various noise performance parameters including the Minimum noise figure and the Minimum Noise Temperature are evaluated. The inclusion of gate-to-drain capacitance is observed to cause significant reduction in the Minimum Noise figure and Minimum Noise Temperature especially at low values of drain voltage, thereby, predicting better noise performance for the device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.4
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• pp.885-890
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• 2014

This paper has presented the change of subthreshold swings for gate oxide thickness of asymmetric double gate(DG) MOSFET, and solved Poisson equation to obtain the analytical solution of potential distribution. The Gaussian function as doping distribution is used to approch experimental results. The symmetric DGMOSFET is three terminal device. Meanwhile the asymmetric DGMOSFET is four terminal device and can separately determine the bias voltage and oxide thickness for top and bottom gates. As a result to observe the subthreshold swings for the change of top and bottom gate oxide thickness, we know the subthreshold swings are greatly changed for gate oxide thickness. Especially we know the subthreshold swings are increasing with the increase of top and bottom gate oxide thickness, and top gate oxide thickness greatly influences subthreshold swings.