• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.10
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• pp.2620-2633
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• 1996

In this paper, a new high-speed local area network using a dual mode switching access (DMSA) protocol implemented on a dual unidirectional bus is described. By utilizing the implicit positionalordering of stations on a unidirectional bus, the proposed system switches between random access mode and the token access model withoug unnecessary delay. Therefore, unlike other hybrid systems such as Buzz-net and Z-net, DMSA does not show a rapid degradation in performance as the load increases. We obtain the average channel utilization and the average access delay by using a simplified analytic model. The numerical results obtained via analysis are compared to the simulation resuls for a partial validation of the approximate model. The performance characteristics of DMSA are superior delay-throughput characteristics at light and medium loads, compared to compared to other LAN systems, and the capability of providing a single active station with full capabity of the channel.

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.632-642
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• 2017

This paper presents an improved approach towards reducing the switching loss of insulated gate bipolar transistors (IGBTs) for a medium-capacity-class power conditioning system (PCS). In order to improve the switching performance, the switching operation is analyzed, and based on this analysis, an improved switching method that reduces the switching time and switching loss is proposed. Compared to a conventional gate drive scheme, the switching loss, switching time, and delay are improved in the proposed gate driving method. The performance of the proposed gate driving method is verified through several experiments.

• Proceedings of the Optical Society of Korea Conference
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• 2000.08a
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• pp.18-19
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• 2000

In this paper, packet error rates of an all-optical packet switching node, which uses a fiber-optic delay-line matched filter as the optical packet header processor, has been calculated for the various optical pulse shapes.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1141-1144
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• 1998

A new design methodology for the shortchannel CMOS IC-package is presented. It is developed by representing the package inductance with an effective lumpedinductance. The worst case maximum-simultaneous-switching noise (SSN) and gate propagation delay due to the package are modeled in terms of driver geometry, the maximum number of simultaneous switching drivers, and the effective inductance. The SSN variations according to load capacitances are investigated with this model. The package design techniques based on the proposed guidelines are verified by performing HSPICE simulations with the $0.35\mu\textrm{m}$ CMOS model parameters.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.265-268
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• 1998

This paper evaluates the VSN(Virtual switch Network) characteristics in the internal call processing of IMT-2000 switching system, which is composed of VSN instead of ATM switch network. In results, internal call establishment delay is increased approximately 5.4msec than the conventional ATM switching system. The evaluated condition is the load 0.8, and the 100km distance between VSNs. It is confirmed that the VSN has the potentiality in the practical implementation.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.281-284
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• 2001

In this paper, we design the Sorting-Banyan network with an efficient buffer and sorting management schema that makes switch be capable of supporting delay sensitive as well as loss sensitive. The proposed switching network is remodeled that based on Batcher-banyan network that have eight input and output ports The structure of designed switching network is constructed of modified banyan network with 2-way routing paths and two plane sorting networks. we have analysed the maximum throughput of the switch, under the uniform random traffic load, the FIFO discipline has increased by about 11% when we compare the switching system with the input buffering system.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.297-300
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• 2001

This paper proposes a sound multicast packet-switching method which can less affect QoS degradation. The method includes a switch fabric with extra switching paths dedicated for multicast packets. Presented also are both a buffering structure and a scheduling algorithm for the proposed method. Simulation analysis for the method shows that the switching delay of unicast packets is decreased even though arrival rate of multicast packets is increased.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.741-748
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• 2005

Power saving module which is consisted of ferroelectric ceramic capacitor and time delay switching circuit was installed into electronic ballast in order to enhance energy efficacy and extend life time of fluorescent lamp. The impedance matching of negative resistance characteristics of F/L was optimized with the characteristics of ferroelectric ceramics capacitor to increase the light efficiency of the electronic ballast. The high efficiency of the electronic ballast was achieved by minimizing wasted power at the filament of F/L during the lighting by using the switching function of time delay circuit from preheating mode to non-preheating mode. The life time of F/L was also extended by eliminating the reverse electromotive force using time delay circuits to minimize the impacts to the filament of F/L from unwanted high voltage peaks during light-up period. As the results, the electronic ballast with the first grade energy efficiency was developed using ferroelectric ceramics and time delay module.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.2
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• pp.83-88
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• 2001

In this paper, System performance parameters such as throughput, blocking probability and delay have been analyzed and expressed as a function of demanding traffic and service terminating probability, and we centers our discussion at particular downlink port of satellite switch which is capable of switching the individual spot beam and processing the information signals in the packet satellite communications with demand assigned multiple access technique. Delay versa throughput as a function of traffic parameters with several service terminating probability can be derived via mathematical formulation and simulation and the relative change of transmission delay was compared.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.73-79
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• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.