• Journal of the Korean Society for Railway
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• v.19 no.4
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• pp.456-467
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• 2016

Wireless Access in Vehicular Environments (WAVE) communication technology, which provides vehicleto-vehicle and vehicle-to-infrastructure communication and offers safe and convenient service, has been developed for application to an Intelligent Transport System (ITS). This paper provides field test results on a study of the feasibility of WAVE technology application to railway communication systems. A test railway communication system based on WAVE technology has been built along the Daebul line and a newly developed EMU. Field tests have been carried out according to the communication function requirements for LTE - R. The test results show that the railway communication system based on WAVE technology meets the functional requirements: maximum transmission length is 730m, maximum transfer delay is 5.69ms, and maximum interruption time is 1.36s; other tests including throughput test, video data transmission test, VoIP data test, and channel switching test also produced results that meets the functional requirements. These results suggest that WAVE technology can be applied to the railway communication system, enabling Vehicle-to-Wayside communication.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.