• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.1091-1100
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• 2004

In this paper, we present a reducing power conswnption of a scheduling for module selection under the time constraint. The proposed low power scheduling executes FDS_LP considering low power to exist the FDS scheduling by inputted the behavioral language. The proposed FDS_LP perfonns lower power consumption with dynamic power which is minimized the switching activity, based on force conception In the time step of module selection, an optimal RT(Register Transfer) library is composed by exploration of the parameters such as power, area, and delay. To find optimal parameters of RT library, an optimal module selection algorithm using Branch and Bound algorithm is also proposed. In the comparison and experimental results, The proposed FDS_LP algorithm reduce maximum power saving up to 23.9% comparing to previous FDS algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1884-1891
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• 2012

In this paper, we design the sliding correlator SS transceiver which supports short message service. We also analyze the PN code acquisition circuit that is essential for spread spectrum receiver. Using Maxplus II tool provided by altera Co., Ltd, we have designed PN code generator, and sliding correlator for PN code acquisition. Then, they have been made into FPGA by way of EPM7064SLC44-10 - a chip of Altera Co., Ltd. Additionally, we have designed delay clock circuit which is faster than the clock of Tx PN clock, designed switching circuit to control the clock rate and data demodulation circuit. The performance of the transceiver is evaluated from the experimental results. Especially, the performance of PN code acquisition accomplished by sliding correlator which is very important to evaluate spread spectrum receiver is evaluated with the comparison of the lock states.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.2116-2118
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• 2000

In the technique of Q-switching, very fast electronically controlled optical shutters can be made by using the electro-optic effect in crystals or liquids. The driver for the Pockels cell must be a high-speed, high-voltage switch which also must deliver a sizeable current. Common switching techniques include the use of vacuum tubes, cold cathode tubes, thyratrons, SCRs, and avalanche transistors. Semiconductor devices such as SCRs, avalanche transistors, and MOSFETs have been successfully employed to drive Pockels cell Q-switch. In this study, a simple driver for the Pockels cell Q-switch was developed by using SCRs, pulse transformer and TTL ICs. The Pockels cell Q-switch which was operated by this driver was employed in pulsed Nd:YAG laser system to investigate the operating characteristics of this Q-switch. And we have investigated the output characteristics of this Q-switch as a function of the Q-switch delay time to Xe flashlamp current on.

• Journal of KIISE:Software and Applications
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• v.27 no.5
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• pp.575-582
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• 2000

Because FIFO thread scheduling used in the existing multithreaded models does not consider locality in programs, it may result in the decrease of the performance of execution, caused by the frequent context switching overhead and delay of execution of relatively short frames. Quantum unit scheduling enhances the performance a little, but it still has the problems such as the decrease in the processor utilization and the longer delay due to its heavy dependency on the priority of the quantum units. In this paper, we propose shortest-frame-first(SFF) thread scheduling algorithm. Our algorithm selects and schedules the frame that is expected to take the shortest execution time using thread size and synchronization information analyzed at compile-time. We can estimate the relative execution time of each frame at compile-time. Using SFF thread scheduling algorithm on the multithreaded models, we can expect the faster execution, better utilization of the processor, increased throughput and short waiting time compared to FIFO scheduling.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.11
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• pp.1689-1700
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• 1993

WDM(Wavelength Division Multiplexing) based-on fixed wavelengths is a new means of utilizing the bandwidth of optical fibers. In this Paper, an improved virtual topology called "(a, $\beta$,${\gamma}$) ShuffleNet " is introdced for designing large-scale WDM switches. The proposed one is an architecture created by vertically stacking x planes of a ($\beta$,${\gamma}$) ShuffleNet in parallel via $\beta$r nodes called "bridge nodes" so that N-by-N(N=(x*$\beta$${\gamma}$*${\gamma}$) switching is achieved based on the self-routing algorithm for each ($\beta$,${\gamma}$) ShuffleNet. With the topological parallelism, in contrast to the conventional virtual topologies, the diameter of 2${\gamma}$ hops can be fixed and high utilization and performance are provided while N increases. Such a scalability characteristic allows to design a growable broadband switch. As for the delay, we show that the traffic locality, due to the topological feature. result in low delay characteristics.lay characteristics.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.2
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• pp.313-322
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• 2000

The ATM Forum has been focusing on flow control mechanism for ABR traffic management. The goal of this activity is to efficiently manage the leftover network bandwidth and fairly distribute it among contending ABR VC so that communication links can be optimally utilized. ABR traffic is difficult to predict traffic shape because it has bursts and variable behavior. Also it's sensitive to lose but not to delay. This behavior makes difficult to UPC function in network and cause of congestion in switch, thus performance is degraded. To resolve this problem, various flow control mechanism has been worked in the ATM Forum. Especially, the rate-based flow control mechanism for ABR traffic has been standardized in the ATM Forum, Sept. 1994. Thus, various flow control mechanism has been working which likes EFCI, ER, VS/VD. VS/VD control is superior than existed ER control because it isolate different networks from each other. In this paper, we propose an expanded VS/VD flow control algorithm and compare with existed VS/VD flow control algorithm. Simulation result shows that this algorithm improve a problem in aspect of delay and fairness.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3B
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• pp.161-167
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• 2007

In this paper, we evaluate the capacity of voice over internet protocol (VoIP) services over high-speed downlink packet access (HSDPA), in which frame-bundling (FB) is incorporated to reduce the effect of relatively large headers in the IP/UDP/RTP layers. Also, a modified proportional pair (PF) packet scheduler design supporting for VoIP service is provided. The main focus of this work is the effect of FB on system outage based on delay budget in radio access networks. Simulation results show that VoIP system performance with FB scheme is highly sensitive to delay budget. We also conclude that HSDPA is attractive for transmission of VoIP if compared to the circuit switched (CS) voice that is used in WCDMA (Release'99).

• Journal of IKEEE
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• v.14 no.3
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• pp.232-235
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• 2010

A 60GHz active phase shifter with 65nm CMOS is presented by replacing passive switches in switched-line type phase shifter with active ones. Active-switch phase shifter is composed of active-switch blocks and passive delay network blocks. The active-switch phase shifter design is compact compare with the conventional vector-sum phase shifter. Active-switch blocks are designed to accomplish required input and output impedances whose requirements are different whether the switch is on or off. And passive delay network blocks are composed of lumped L,C instead of normal microstrip line to reduce the size of the circuit. An 1-bit phase shifter is fabricated by TSMC 65nm CMOS technology and measurement results present -4dB average insertion loss and 120 degree phase shift at 65GHz.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.7
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• pp.1-11
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• 2002

This paper proposes that an efficient routing entry sending method between routing controller FE. based on this method, we organize IP VPN support method based on MPLS network and design MPLS-VPN service control module, MPLS-VPN processing, VPN group configuration and LSP setup processing. We evaluate the performance about the VPN based on proposed MPLS, at the result of evaluation. We figure out that based on proposed IPC method, lost packets number reduces and delay increases more slowly in case of VPN based on MPLS comparing with the VPN based on ATM which has rapid delay increasement. Therefore we confirm that the VPN based on MPLS has high speed of packet processing and high utilization of buffers through the performance evaluation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.1-10
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• 1998

The advent of deep submicron technologies in the age of portable electronic systems creates a moving target for CAB algorithms, which now need to reduce power as well as delay and area in the existing design methodology. This paper presents a resynthesis algorithm for logic decomposition on mapped circuits. The existing algorithm uses a Huffman encoding, but does not consider glitches and effects on logic depth. The proposed algorithm is to generalize the Huffman encoding algorithm to minimize the switching activity of non-critical subcircuits and to preserve a given logic depth. We show how to obtain a transition-optimum binary tree decomposition for AND tree with zero gate delay. The algorithm is tested using SIS (logic synthesizer) and Level-Map (LUT-based FPGA lower power technology mapper) and shows 58%, 8% reductions on power consumptions, respectively.