• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.8
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• pp.500-508
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• 2004

This paper presents a new sensorless vector control system for high performance induction motor drives fed by a matrix converter with non-linearity compensation and disturbance observer. The nonlinear voltage distortion that is caused by commutation delay and on-state voltage drop in switching device is corrected by a new matrix converter modeling. The lumped disturbances such as parameter variation and load disturbance of the system are estimated by the radial basis function network (RBFN). An adaptive observer is also employed to bring better responses at the low speed operation. Experimental results are shown to illustrate the performance of the proposed system.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.4
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• pp.246-255
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• 2000

This paper deals with a novel full digital control method of the three-phase PWM inverter for UPS. The voltage and current of output filter capacitor as state variables are the feedback control input. In addition, a double deadbeat control consisting of a d-q current minor loop and a d-q voltage major loop, both with precise decoupling, have been developed. The switching pulse width modulation based on SVM is adopted so that the capacitor current should be exactly equal to its reference current. In order to compensate the calculation time delay, the predictive control is achieved by the current·voltage observer. The load prediction is used to compensate the load disturbance by disturbance observer with deadbeat response. The experimental results show that the proposed system offers an output voltage with THD less than 2% at a full nonlinear load.

• Proceedings of the KIEE Conference
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• 1994.11a
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• pp.138-140
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• 1994

In this paper, a three-phase active power filter using voltage- source PWM converter is designed to eliminate the harmonics and compensate the reactive power in the ac side. The predictive current control method is adopted, which provides constant switching frequency and low current ripple but has inherently one sampling error between the command and the actual current. Here we propose the algorithm which corrects this delay time. The converter voltage obtained from this current control can be accomplished by the space vector modulation method at a voltage-type converter. All control sequences of active filter is executed by a DSP which is designed to calculate floating points at very hight speed. Finally, the validity of this filter using the predictive current control method is demonstrated through experimental results.

• Proceedings of the KIEE Conference
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• 1994.11a
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• pp.147-149
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• 1994

Binary control with integral COFB is presented to alleviate the chattering. Binary control system consists of the main loop and the external loop which transforms the gain of main loop smoothly, and can generate the continuous control input under the existence of the delay and the switching frequency limitation of the controller. Therefore, it has the properties of chattering alleviation, in addition, advantages of the conventional variable structure control. To confirm the validity of the developed controller, position control of brushless DC motor with binary controller as a position controller is performed.

• Journal of Power Electronics
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• v.19 no.3
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• pp.613-624
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• 2019

Digital current control techniques are an attractive option for DC-DC converters. In this paper, a digital predictive peak current control algorithm is presented for buck converters that allows the inductor current to track the reference current in two switching cycles. This control algorithm predicts the inductor current in a future period by sampling the input voltage, output voltage and inductor current of the current period, which overcomes the problem of hardware periodic delay. Under the premise of ensuring the stability of the system, the response speed is greatly improved. A real-time parameter identification method is also proposed to obtain the precision coefficient of the control algorithm when the inductance is changed. The combination of the two algorithms achieves adaptive tracking of the peak inductor current. The performance of the proposed algorithms is verified using simulations and experimental results. In addition, its performance is compared with that of a conventional proportional-integral (PI) algorithm.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.1
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• pp.9-17
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• 2022

The series-connected semiconductor devices structure is one way to achieve a high voltage rating. However, a problem with voltage imbalance exists in which different voltages are applied to the series-connected switches. This paper proposed a new voltage balancing technique that controls the turn-off delay time of the switch by adding one bipolar junction transistor to the gate turn-off path. The validity of the proposed method is proved through simulation and experiment. The proposed active gate driver not only enables voltage balancing across a variety of current ranges but also has a greater voltage balancing performance compared with conventional RC snubber methods.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.78.2-78.2
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• 2012

최근 PRAM의 집적도 향상 및 3차원 적층에 의한 메모리 용량 향상을 위해 셀 선택 스위치로서 박막형 Ovonic Threshold Switching (OTS) 소자를 적용한 Cross bar 구조의 PRAM이 제안된 바 있다. OTS 소자는 비정질 칼코지나이드를 핵심층으로 하는 2단자 소자로서 고저항의 Off 상태에 특정 값 (문턱스위칭 전압) 이상의 전압을 가해주면 저저항의 On 상태로 바뀌고 다시 특정 값 (유지전압) 이하로 전압을 감소시킴에 따라 고저항의 Off 상태로 복원하는 특성을 갖는다. 셀 선택용 스위치로 적용되기 위해서는 핵심적으로 On-Off 상태간의 가역적인 변화 중에도 재료가 비정질 구조를 안정하게 유지해야 하며 전기적으로는 Off 상탱의 저항이 크고 또한 전류값의 점멸비가 커야 한다. GeSe는 이원계 재료로서 단수한 구성에도 불구하고 OTS 소자가 갖추어야할 기본적인 특성을 가지는 것으로 알려져 있다. 본 연구에서는 GeSe로 구성된 OTS 재료에 경원소인 질소를 첨가하여 비정질 상태의 안정성과 소자특성의 개선 효과를 조사하였다. RF-puttering 시 Ar과 $N_2$의 혼합 Gas를 사용하여 조성이 $Ge_{62}Se_{38}$ ($N_2$ : 3%)인 박막을 제작하여 DSC를 통해 결정화온도(Tx)를 확인하였고, $N_2$ gas의 함유량이 각각 1 %, 2 %, 3 %인 $Ge_{62}Se_{38}$인 박막을 전극의 접촉 부 면적이 $10{\times}10\;{\mu}m^2$인 cross-bar 구조의 소자로 제작하여 Threshold switching voltage ($V_{th}$), Delay time ($t_d$), $I_{on}/I_{off}$ 그리고 Endurance 특성을 평가하였다. DSC 분석 결과 $N_2$ 가 3 % 첨가된 GeSe 박막은 Tx가 $371^{\circ}C$에서 $399^{\circ}C$로 증가되었다. $N_2$가 1% 첨가된 GeSe 소자를 측정한 결과 $V_{th}$의 변화 없는 가운데 $I_{on}/I_{off}$이 약 $2{\times}10^3$에서 $5{\times}10^4$로 향상되었다. Endurance 특성 역시 $10^4$에서 $10^5$번으로 향상되었다. $t_d$의 경우 비정질 상태의 저항 증가로 인해 약 50% 증가되었다. 이러한 $N_2$의 첨가로 인한 비정질 GeSe 박막의 변화 원인에 대한 분석 결과를 소개할 예정이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12B
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• pp.1050-1057
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• 2008

Wireless Mesh Networks (WMNs) have recently become a hot issue to support high link capacity in wireless access networks. The IEEE 802. I 1 standard which is mainly used for the network interface technology in WMNs supports up to 3 or 12 multiple channels according to the IEEE 802.11 specification. However, two important problems must be addressed when we design a channel assigmnent algorithm: channel dependency problem and channel scanning delay. The former occurs when the dynamic channel switching of an interface leads to the channel switching of other interfaces to maintain node connectivity. The latter happens per channel switching of the interface, and affects the network performance. Therefore, in this paper, we propose the Distance-Based Channel Assigmnent (DB-CA) scheme for multi-channel WMNs to solve such problems. In DB-CA, nodes just perform channel switching without channel scanning to communicate with neighboring nodes that operate on different channels. Furthermore, DB-CA minimizes the interference of channels being used by nodes near the gateway in WMNs. Our simulation results show that DB-CA achieves improved performance in WMNs.

• Journal of KIISE:Information Networking
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• v.33 no.1
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• pp.38-48
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• 2006

For extending of hot-spot of WLAN, (2) proposes internetworking scheme between wireless LAN (WLAN) and mobile ad-hoc network (MANET), which employ the same layer-2 protocol with different mode. Compared to internetworking schemes between UMTS (Universal Mobile Telecommunications Systems) and WLAN (3-4), the scheme from (2) has relatively low overhead and latencies because WLAN and MANET are physically and logically similar to each other. However, the mode switching algorithm proposed in r2] for internetworking between WLAN and MANET only considers signal strength and determines handoff, and mobile nodes following a zigzag course in pollution area may perform handoff at short intervals. Furthermore, (2) employs mobile IPv6 (MIPv6) at base, which brings still high delay on handoff and overhead due to signal message exchange. In this paper, we present optimized internetworking scheme between WLAN and MANET, modified from (2). To settle ping-pong handoff from (2), we propose adaptive mode switching algorithm. HMIPv6 is employed for IP connectivity and mobility service in WLAN, which solves some shortcomings, such as high handoff overhead and vulnerable security. For routing in MANET, OLSR is employed, which is a proactive Protocol and has optimally reduced signal broadcasting overhead. OLSR operates with current P protocol compatibly with no change or modification. The proposed internetworking scheme based on adaptive mode switching algorithm shows better performance than scheme from (2).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.