• Title/Summary/Keyword: switching delay

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Letters Current Quality Improvement for a Vienna Rectifier with High-Switching Frequency (높은 스위칭 주파수를 가지는 비엔나 정류기의 전류 품질 개선)

  • Yang, Songhee;Park, Jin-Hyuk;Lee, Kyo-Beum
    • The Transactions of the Korean Institute of Power Electronics
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    • v.22 no.2
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    • pp.181-184
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    • 2017
  • This study analyzes the turn-on and turn-off transients of a metal-oxide-semiconductor field-effect transistor (MOSFET) with high-switching frequency systems. In these systems, the voltage distortion becomes serious at the output terminal of a Vienna rectifier by the turn-off delay of the MOSFET. The current has low-order harmonics through this voltage distortion. This paper describes the transient of the turn-off that causes the voltage distortion. The algorithm for reducing the sixth harmonic using a proportional-resonance controller is proposed to improve the current distortion without complex calculation for compensation. The reduction of the current distortion by high-switching frequency is verified by experiment with the 2.5-kW prototype Vienna rectifier.

Analysis Simultaneously Switching Density Using Ring Oscillator (Ring Oscillator를 이용한 신호의 동시 스위칭 밀도 분석)

  • Jeong, Sang-Nam;Baeg, Sang-Hyeon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.9
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    • pp.79-84
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    • 2008
  • Switching speeds increase in both frequency and the transition rate of edges. Inadequate forecast for simultaneous switching signals may cause designing the power planes without sufficient current capability. The delay of critical signals in a chip can be therefore inadvertently increased and the situation makes it hard to debug issues. It is important to find the degree of increased switching during the debugging or chip characterization phases. This paper proposes the interpolation method to predict the switching density in a design. The interpolation was achieved by utilizing the dependencies between switching frequency and the delay appeared in a ring oscillator. The ring oscillator was primarily used to accumulate the effects of the ground bounce by higher switching. The result of interpolation was demonstrated using DongBu Hitec 0.18um CMOS technology.

An Analytical Switching-Dependent Timing Model for Multi-Coupled VLSI Interconnect lines (디커플링 방법을 이용한 RC-Coupled 배선의 해석적 지연시간 예측 모델)

  • Kim, Hyun-Sik;Eo, Yung-Seon;Shim, Jong-In
    • Proceedings of the IEEK Conference
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    • 2004.06b
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    • pp.439-442
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    • 2004
  • Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

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The Analysis and Compensation of Switching Time Delay in PWM Inverters (PWM인버터에서 스위칭시간지연이 미치는 효과의 분석 및 그 보상)

  • 박민호;홍순찬;정승기
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.40 no.1
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    • pp.58-66
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    • 1991
  • In inverters, time delays are inserted in the switching signals to prevent the dc lind shortage. This causes detrimental effects on the performance of the inverters, that is, the fundamental voltage drop and the generation of low order harmonics. This paper derives simple formula to describe the time delay effects in PWM inverters, where the effects may become significant because of relatively high switching frequencies. To compensate the tice delay effects, this paper presents two methods which are suitable for sinusoidal PWM and memory-based PWM respectively. Both are simple, easy to implement, and are shown to be effective, through the experiments, in improving the output waveform of PWM inverters.

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The Driving Circuit Design for ZVS Full-Bridge Converter with 1st Order Delay Circuit (1차 지연회로를 사용한 ZVS Full-Bridge 컨버터 구동회로 설계)

  • Cho, Nae-Soo;Choi, Youn-Ho;Yoon, Kyung-Sup;Koo, Bon-Ho;Kwon, Woo-Hyen
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.59 no.3
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    • pp.569-574
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    • 2010
  • The full bridge converter have been used for high power system that is needed to switch the big current. So, EMI and stability problem is occurred. The Soft switching method is the solution to solve the above problem, But implementation of soft switching(ZVS: Zero Voltage Switching) is so complicate and expensive because of the DSP MCU and shift circuit. In this paper, we introduce the technical method for driving circuit of ZVS full bridge converter with 1st order delay circuit and logic elements. The realization of this method is so simple and cheap. The effectiveness of the proposed circuit is verified by experimental results.

Current Control Scheme of High Speed SRM Using Low Resolution Encoder

  • Khoi, Huynh Khac Minh;Ahn, Jin-Woo;Lee, Dong-Hee
    • Journal of Power Electronics
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    • v.11 no.4
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    • pp.520-526
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    • 2011
  • This paper presents a balanced soft-chopping circuit and a modified PI controller for a high speed 4/2 Switched Reluctance Motor (SRM) with a 16 pulse per revolution encoder. The proposed balanced soft-chopping circuit can supply double the switching frequency in the fixed switching frequency of power devices to reduce current ripple. The modified PI controller uses maximum voltage, back-emf voltage and PI control modes to overcome the over-shoot current due to the time delay effect of current sensing. The maximum voltage mode can supply a fast excitation current with consideration of the hardware time delay. Then the back-emf voltage mode can suppress the current over-shoot with consideration of the feedback signal delay. Finally, the PI control mode can adjust the phase current to a desired value with a fast switching frequency due to the proposed balanced soft-chopping technology.

Determination of Importance of Software Blocks for Improving Quality of Service in Switching System (교환시스템의 서비스 품절수준 향상을 위한 소프트웨어 블록의 중요도 결정)

  • 조재균
    • The Journal of Information Systems
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    • v.8 no.1
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    • pp.93-108
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    • 1999
  • The switching system is designed and developed to satisfy the performance design objectives recommended by ITU for call processing capacity and quality of service(QOS), etc. When the results by actual measurement at the system testing phase do not satisfy the performance design objectives, however, an effort is required to improve the performance. This paper presents a method for improving QOS by modifying the application programs for the switching system. In the proposed method, the sequence chart related to a delay time for call connection is modelled using PERT(Program Evaluation and Review Technique) network. Then, the criticality index of a message is calculated using Monte Carlo simulation to evaluate which message's processing time to decrease in order to decrease the delay time and thus to improve QOS. The criticality index of a block is also calculated to identify those software blocks that significantly contribute to the delay time.

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Fast Link Switching Scheme for LED-ID System

  • Trung, Bui Minh;Uddin, Muhammad Shahin;Chowdhury, Mostafa Zaman;Nguyen, Tuan;Jang, Yeong-Min
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.12B
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    • pp.1586-1594
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    • 2011
  • LED-ID (light emitting diode - identification) technology is the new paradigm in the identification technology environment. LED-ID system typically needs line of sight (LOS) that supports narrow FOV transceivers links to achieve high data rate. On the other hand, narrow FOV reduces the coverage area. Therefore, the number of tags is increased significantly to cover the whole area. In this case number of link switching is increased when the reader moves within whole coverage area. Link switching delay is the important factor for the moving reader to maintain the communication with high data rate and better QoS. In this paper we propose in literature a new link switching scheme and measure the link switching delay time for LED-ID system. The simulation results show that the proposed link switching scheme is a possible candidate for multi-tag LED-ID system.

The Effects of Internet Fashion Consumer's Impulse Buying Tendency on Positive and Negative Purchasing Behaviors (인터넷 패션 소비자의 충동구매성향이 긍정적, 부정적 구매행동에 미치는 영향)

  • Lee, Eun-Jin
    • Fashion & Textile Research Journal
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    • v.13 no.4
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    • pp.511-522
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    • 2011
  • This study analyzed the effects of internet fashion consumer's impulse buying tendency on positive and negative purchasing behaviors. A survey was conducted from October 1 to December 15 in 2010, and 407 responses from internet fashion consumers who made impulse purchases on the internet at least once for the last 6 months were used in the data analysis. As a result, the impulse buying tendency of internet fashion consumers was classified into pure impulse buying, reminder impulse buying, suggestion impulse buying, and stimulus impulse buying. The positive purchasing behaviors such as repurchase intention and purchase satisfaction were influenced by the impulse buying tendency. The all factors of impulse buying tendency had an effect on repurchase intention, while purchase satisfaction was influenced by the reminder impulse buying, suggestion impulse buying, and stimulus impulse buying. The negative purchasing behaviors were classified into delay in decision making and switching intention of purchase. The delay in decision making was influenced by the stimulus impulse buying, suggestion impulse buying, and reminder impulse buying. Also, the reminder impulse buying, suggestion impulse buying and pure impulse buying had an effect on switching intention of purchase. In addition, there were significant differences in the impulse buying tendency and delay in decision making between male and female internet fashion consumers.

Switching Characteristics of Transistor & IC-Version of Oscillator (트랜지스터의 스위칭 특성과 IC화 할 수 있는 발진회로)

  • 김경희
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.17 no.6
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    • pp.86-92
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    • 1980
  • This paper dealt with an oscillator which can be integrated and 1 he switching characteristics of the transistor as a component of multistage switching circuits . The switching characteristics were analyzed by utilizing the base voletare and the charactistics of the minit step function. Taking the storage time of the transistor into consideration, the transistor is considered as a time delay device, and an integrable time delay circuit an osicillator are realized.

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