• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.10
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• pp.41-50
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• 1993

This paper describes the fabrication process and electrical characteristics of PSA (Polysilicon Self-Align) bipolar transistors with a thin base width of 1100.angs.. To realize this shallow junction depth, one-step rapid thermal annealing(RTA) technology has been applied instead of conventional furnace annealing process. It has been shown that the series resistances and parasitic capacitances are significantly reduced in the device with emitter area of 1${\times}4{\mu}m^{2}$. The switching speed of 2.4ns/gate was obtained by measuring the minimum propagation delay time in the I$^{2}$L ring oscillator with 31 stages.

• 연구논문집
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• s.27
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• pp.141-151
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• 1997

Recently, the importance of electro-multifunction control valve which is digital control valve is increasing day after day. This is due to the demand of that the current industrial world wants the valve having simpler control circuit and higher operation reliability. It is the PWM controlled high speed electronic valve that satisfies the damands of current industrial world. But, the PWM controlled high speed electronic valve has some non-linearity characteristics like as the delay time of switching and the pressure oscillation phenomenon. These characteristics are an obstacle for the control of high speed & high efficiency in control system. Therefore, in this study, we set the studying purpose on analysis of parameter characteristics in solenoid, and on establishment of optimum design technique in high speed solenoid.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.350-353
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• 1999

In this paper, a new simple control method for active power filter which can realized the complete compensation of the harmonic currents is proposed. In the proposed scheme, a compensating current reference generator employing lossless resonato implemented by a DSP(Digital Signal Processor) is introduced. Deadbeat control is employed to contro the active power filter. The switching pulse width based SVM(Space Vector Modulation) is adopted so that the current of active power filter is been exactly equal to its reference at the next sampling instant. To compensate the computation delay of digital controller, the prediction of current is achieved by the current observer with deadbeat response.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.2
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• pp.123-129
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• 2000

This paper proposes a novel current control method of three-phase PWM rectifiers using estimated currents without phase current sensors. The phase currents are reconstructed from switching states of the rectifier and the measured dc output currents. To eliminate the calculation time delay effect of the microprosessor, the current at the next sampling instant are predicted by a predictive state observer and then are used for feedback control. Experimental results show that the control performance of the proposed system is almost the same as that of the phase current sensor-based system.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.581-582
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• 2008

This paper describes novel bootstrapped CMOS differential logic family operating at near-Vth supply voltage. The proposed logic family provides improved switching speed by utilizing voltage bootstrapping for the supply voltage approaching device thresholds. The circuit is configured as differential structure having single bootstrapping capacitor, minimizing area overhead and providing complete logic composition capability. A 64-bit adder designed using the proposed technique in a 0.18um CMOS process provides up to 79% improvement in terms of power-delay product as compared to the conventional adder designed with DCVS.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.113-116
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• 1999

This paper presents a hardware architecture of AAL(ATM Adaptation Layer) type 2 switch. The proposed architecture can assign and configure maximum AAL2 CID limit. AAL2 is the protocol which has been recommended by ITU-T and ATM-Forum for low bit rate delay sensitive services. The architecture assumes 155 Mbps STM-1/STS-3c physical interface, maximum VCC can be 64K connections. It can support maximum 16,384M AAL2 connections. For efficient use of peripheral memory, a concept of segment address was proposed. The proposed AAL2 switch hardware architecture can be used in ATM network as a standalone server or embedded module in a ATM switching system.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.1209-1218
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• 1995

In this paper, we develope an ATM switch simulator in order to evaluate the HAN/B-ISDN ATM switch currently being developed by ETRI. It models the basic cell switching functions of the target ATM switch with priority control and multicasting features and it also supports such various traffic models as random or bursty traffic, balanced or unbalanced traffic, multicast traffic models. Using this simulator, we can evaluate the performances of the ATM switch in terms of various performance indices, i.e. cell delay, cell loss probability, etc., and this simulator can be utilized in the system parameter tunings such as the common buffer size and address buffer size.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.102-106
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• 2003

This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and by eliminating redundant transitions. It also minimizes the data-to-output latency by reducing the height of transistor stack on the critical path. Moreover, DETNKFF allows negative setup time to provide useful attribute of soft clock edge by incorporating the pulse-triggered operation. The proposed flip-flop was designed using a $0.35{\;}\mutextrm{m}$ CMOS technology. The simulation results indicate that, for the typical input switching activity of 0.3, DETNKFF reduces power consumption by as much as 21 %. Latency is also improved by about 6 % as compared to the conventional flip-flop. The improvement of power-delay product is also as much as 25 %.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.544-547
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• 2003

The purpose of this paper is to develop the straightforward design guidelines of PD/PID speed controller for Industry servo drives with plug and play concept. The controller gains are uniquely determined from the current control loop dynamics, speed loop delay, and mechanical parameters. In order to eliminate the mechanical friction uncertainties, an automatic PD/PI control mode switching algorithm Is introduced using online spectrum analysis of motor torque command. The dynamic performance of the proposed scheme assures a fast tracking response curve with minimal oscillation and settling time over the whole operating conditions. For comprehensive comparison of conventional PI control scheme, extensive test is carried out on actual servo system.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.252-257
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• 1998

Two-stage power factor correction (PFC) converter with a single PWM controller for universal input voltage (90-264V) is proposed. It consists of a power factor pre-regulator cascaded by a DC/DC converter as in a conventional two-stage approach. However, a single PWM controller is used as in a single-stage, single-switch PFC approach. The switch in the PFC part is synchronized with the switch in the DC/DC converter with a fixed switching frequency. Employing an adaptive delay scheme the switch in the PFC part is controlled to limit the energy storage capacitor voltage within a designed range for the optimum efficiency, and to reduce input current harmonic distortion. The experimental results obtained on a 200W (5V/40A) prototype PFC converter are given to verify the effectiveness of the proposed control method.