• Journal of Electrical Engineering and Technology
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• v.13 no.6
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• pp.2479-2484
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• 2018

The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.42 no.2
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• pp.7-14
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• 2005

This paper presents a method to reduce torque ripple of brushless DC motor by compensating phase delay due to winding inductance. For considering torque ripple comes from the phase winding inductance, torque equation of one phase is derived as Fourier series that is function of the delay. From the equation, also the resultant equation that the current delay is compensated is derived. It is validated that the compensated torque has a form of Fourier series for rectangular wave that is ideal torque, and torque ripple is reduced, consequently. Experimental method for the compensation is realized by replacing switching pattern of inverter by pattern of compensated rotor position. The effectiveness of the proposed method to reduce torque ripple has been demonstrated by the simulation and experimental results using 3 phase 4 pole brushless DC moor.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.23-30
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• 2006

This paper presents design andd verification of a circuit that improves the control-operation problems of Stored Program Optical Computer (SPOC), which is an optical computer using $LiNbO_3$ optical switching element. Since the memory of SPOC takes the Delay Line Memory (DLM) architecture and instructions that are needless of operands should go though memory access stages, SPOC memory have problems; it takes immoderate access time and unnecessary operations are executed in Arithmetic Logical Unit (ALU) because desired operations can't be selectively executed. In this paper, improvement on circuit has been achieved by removing the memory access of instructions that are needless of operands by decoding instructions before locating operand. Unnecessary operations have been reduced by sending operands to some specific operational units, not to all the operational units in ALD. We show that total execution time of a program is minimized by using the Dual Instruction Register(DIR) architecture.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.1
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• pp.43-51
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• 2010

This paper proposes an analysis of voltage delay and compensation for current control in H-Bridge Multi-Level (HBML) inverters for a medium voltage motor drive with vector control. It is shown that the expansion and modularization capability of the HBML inverter is improved in case of using Phase-Shifted Pulse Width Modulation (PSPWM) since individual inverter modules operate more independently. But, the PSPWM of HBML has a phase difference between reference voltage and real voltage, which can cause instability in the current regulator at high speed where the ratio of the sampling frequency to the output frequency is insufficient. This instability of the current regulator is removed by adding a proposed method which compensate a phase difference between reference voltage and real voltage. The proposed method is suitable for HBML inverter controlled by PSPWM with low switching frequency and high speed motor drive. The validity of the proposed method is verified experimentally on 6,600[V] 1,400[kW] induction motor fed by an 13-level HBML inverter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.243-251
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• 1990

In this paper, the performances of bandwidth allocation strategies for wideband ISDN have been studied through the computer simulation. In general, the performance of multichannel bandwidth allocation method is superior to that of single channel bandwidth allocation method with respect to the throughtput, delay and blocking probability. Also, when the FIFO service scheme is used, it is shown that the throughput, delay characteristics and blocking probability for each traffic are almost similar. On the other hand, the priority service scheme being used, the performances of traffic with high priority are much better than that of traffic with low priority in the view of throughput, delay and blocking probability. Finally, for the FIFO and priority service disciplines, it can be seen that the multichannel bandwidth allocation method is more suitable than the single channel bandwidth allocation strategy in the case of serving various traffic.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.10-16
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• 2016

For higher reliability against a link failure of a control network in railway vehicles, a recovery mechanism is needed. We introduce a problem that, when a link failure occurs in a ring-topology control network, a node may experience a significant increase of transmission delay depending on its relative position within the network. We then propose two mechanisms to solve this problem: (1) differentiating and prioritizing node traffic in forwarding; and (2) switching some nodes to a backup bus-topology network. Our simulation study shows that, while the first mechanism achieves a limited gain by only compensating queuing delay, the second one gets a sufficient gain which is impacted by the number of nodes switched to the bus network.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.2
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• pp.37-43
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• 1999

Modules of the system that requires large capacity and high-speed information processing are implemented in the form of MCM that allows high-speed data processing, high density circuit integration and widely applied to such fields as ATM, GPS and PCS. Hence we developed the ATM switching module that is consisted of three chips and 2.48 Gbps data throughput, in the form of 10 multi-layer by Cu/Photo-BCB and 491pin PBGA which size is $48 \times 48 \textrm {mm}^2$. hnologies required for the development of the MCM includes extracting parameters for designing the substrate/package through the interconnect characterization to implement the high-speed characteristics, thermal management at the high-density MCM, and the generation of the testability that is one of the most difficult issues for developing the MCM. For the development of the ATM Switching MCM, we extracted signaling delay, via characteristics and crosstalk parameters through the interconnect characterization on the MCM-D. For the thermal management of 15.6 Watt under the high-density structure, we carried out the thermal analysis. formed 1.108 thermal vias through the substrate, and performed heat-proofing processing for the entire package so that it can keep the temperature less than $85^{\circ}C$. Lastly, in order to ensure the testability, we verified the substrate through fine pitch probing and applied the Boundary Scan Test (BST) for verifying the complex packaging/assembling processes, through which we developed an efficient and cost-effective product.

• Journal of applied mathematics & informatics
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• v.17 no.1_2_3
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• pp.737-746
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• 2005

Average memory occupancy and congestion in computer system or communication system may be reduced further if new jobs are admitted only when the number of jobs queued at CPU is below a certain threshold, run queue cutoff (RQ). In our previous paper we showed that response time of a job is invariant with respect to RQ if jobs do not communicate each other. In this paper, we prove that the invariance property by considering the evolution of the queue lengths as point processes. We also present an approximate method for the delay due to context switching under time slicing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2B
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• pp.144-156
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• 2003

Internet/Intranet has been continuously enhanced by new emerging IP technologies such as differentiate service(DiffServ), IPSec(IP Security) and MPLS(Multi-protocol Label Switching) traffic engineering. According to the increased demands of various real-time multimedia services, ISP(Internet Service Provider) should provide enhanced end-to-end QoS(quality of service) and security features. Therefore, Internet and Intranet need the management functionality of sophisticated traffic engineering functions. In this paper, we design and implement the performance management functionality for the guaranteed end-to-end QoS provisioning on MPLS-based VPLS(Virtual Private LAN Service). We propose VPLS OAM(Operation, Administration and Maintenance) for efficient performance management. We focus on a scheme of QoS management and measurement of QoS parameters(such as delay, jitter, loss, etc.) using VPLS OAM functions. The proposed performance management system also supports performance tuning to enhance the provided QoS by re-adjusting the bandwidth of LSPs for VPLS. We present the experimental results of performance monitoring and analysis using a network simulator.

• ETRI Journal
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• v.25 no.1
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• pp.34-40
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• 2003

This paper considers a TMN-based management system for the management of public ATM switching networks using a four-level hierarchical structure consisting of one network management system, several element management systems, and several agent-ATM switch pairs. Using Jackson's queuing model, we analyze the effects of one TMN command on the performance of the component ATM switch in processing local calls. The TMN command considered is the permanent virtual call connection. We analyze four performance measures of ATM switches- utilization, mean queue length and mean waiting time for the processor directly interfacing with the subscriber lines and trunks, and the call setup delay of the ATM switch- and compare the results with those from Jackson's queuing model.