• Journal of Communications and Networks
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• 제18권4호
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• pp.600-609
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• 2016

In this paper, we propose a two-stage base station (BS) sleeping scheme to save energy consumption in cellular networks. The BS sleeping mode is divided into a light sleeping stage and a deep sleeping stage according to whether there is a user in the BS's coverage. In the light sleeping stage, a BS will retain its coverage and frequently switch between the on state and the doze state according to the service characteristics. While in the deep sleeping stage analysis, the BS will shut down its coverage, and neighbor BSs will patch the coverage hole. Several closed-form formulas are derived to demonstrate the power consumption in each sleeping stage and the stage switching conditions are discussed to minimize the average power consumption. The average traffic delay caused by BS sleeping and the average deep sleeping rate under a given traffic load have also been studied. In addition, it is shown that BS sleeping is not always possible because of the limited quality of service (QoS) requirements. Simulation results show that the proposed scheme can effectively reduce the average BS power consumption, at the cost of some extra traffic delay. In summary, our proposed framework provides an essential understanding of the design of future green networks that aim to take full advantage of different stages of BS sleeping to obtain the best energy efficiency.

• The Transactions of the Korea Information Processing Society
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• 제6권10호
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• pp.2764-2771
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• 1999

ATM has recently received much attention because of its high capacity, its bandwidth scalability, and its ability to support multiservice traffic. However, ATM is connection oriented whereas the vast majority of modern data networking protocols are connectionless. The alternative to support current service on ATM will be a router with attached switching hardware that has the ability to cache routing decisions. In this paper, we described the router using a switch and simulated the performance. From the results of the simulation, the routing delay was decreased as the number of flow channels. Cell-delay was shortest at 30,000 cell-time when the keeping time of a flow channel was. The line utilization was rapidly decrease when a flow-setup time is 20 30 cell-time. The results of this simulation could be applied to predict the performance of the router using ATM switch.

• Proceedings of the KIEE Conference
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 B
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• pp.1480-1482
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• 2005

The major causes of power quality deterioration are harmonic current through semiconductor switching device, due to use of nonlinear loads such as diodes rectifier or thyristor rectifiers. In response to this concerns, this paper presents a new control method of single-phase active power filter(APF) for the compensation of harmonic current components in nonlinear loads. In order to make the complex calculation to be possible, the single-phase system that has two phases was made by constructing a imaginary second-phase giving time delay to load currents. In the conventional method, a imaginary-phase lagged to the load current T/4(here T is the fundamental cycle) was made. But in this proposed method, the new signal, which has the delayed phase through the filter, using the phase-delay property of low-pass filter, was used as the second phase. As this control method is applied to the system of single phase, an instantaneous calculation was done rather by using the rotating reference frames that synchronizes with source-frequency than by applying instantaneous reactive power theory that uses the conventional fixed reference frames.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제49권1호
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• pp.15-24
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• 2012

In this paper, we suggest the dynamic-response-free SMPS using a new high-resolution DPWM generator based on switched-capacitor delay technique. In the proposed system, duty ratio of DPWM is controlled by voltage slope of an internal capacitor using switched-capacitor delay technique. In the proposed circuit, it is possible to track output voltage by controlling current of the internal capacitor of the DPWM generator through comparison between the feedback voltage and the reference voltage. Therefore the proposed circuit is not restricted by the dynamic-response characteristic which is a problem in the existing SMPS using the closed-loop control method. In addition, it has great advantage that ringing phenomenon due to overshoot/undershoot does not appear on output voltage. The proposed circuit can operate at switching frequencies of 1MHz~10MHz using internal operating frequency of 100 MHz. The maximum current of the core circuit is 2.7 mA and the total current of the entire circuit including output buffer is 15 mA at the switching frequency of 10 MHz. The proposed circuit has DPWM duty ratio resolution of 0.125 %. It can accommodate load current up to 1 A. The maximum ripple of output voltage is 8 mV. To verify operation of the proposed circuit, we carried out simulation with Dongbu Hitek BCD $0.35{\mu}m$ technology parameter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제41권1호
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• pp.81-90
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• 2004

The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique . based on m-block partition is introduced in this paper. By the m-block partition algorithm, the dependencies among groups of state variables are minimized and switching activity is further reduced by assigning the codes of the states in the same group considering the state transition probability among the states. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on state variables. It is inherently contradictory problem to optimize the testability and power consumption simultaneously, however our new state assignment technique is able to achieve high fault coverage with less number of scan nfp flops by reducing the number of feedback cycles while the power consumption is kept low upon the low switching activities among state variables. Experiment shows drastic improvement in testabilities and power dissipation for benchmark circuits.

• Journal of Mechanical Science and Technology
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• 제19권3호
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• pp.778-791
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• 2005

A novel pneumatic artificial muscle actuator (PAM actuator), which has achieved increased popularity to provide the advantages such as high strength and high power/weight ratio, low cost, compactness, ease of maintenance, cleanliness, readily available and cheap power source, inherent safety and mobility assistance to humans performing tasks, has been regarded during the recent decades as an interesting alternative to hydraulic and electric actuators. However, some limitations still exist, such as the air compressibility and the lack of damping ability of the actuator bring the dynamic delay of the pressure response and cause the oscillatory motion. Then it is not easy to realize the performance of transient response of pneumatic artificial muscle manipulator (PAM manipulator) due to the changes in the external inertia load with high speed. In order to realize satisfactory control performance, a variable damper-Magneto­Rheological Brake (MRB), is equipped to the joint of the manipulator. Superb mixture of conventional PID controller and a phase plane switching control method brings us a novel controller. This proposed controller is appropriate for a kind of plants with nonlinearity, uncertainties and disturbances. The experiments were carried out in practical PAM manipulator and the effectiveness of the proposed control algorithm was demonstrated through experiments, which had proved that the stability of the manipulator can be improved greatly in a high gain control by using MRB with phase plane switching control method and without regard for the changes of external inertia loads.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제23권7호
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• pp.1777-1784
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• 1998

The packet error rates of an optical packet switching node with an optical address processor using an EDFA in order to detect M-ary correlation pulses at a fiber-optical delay line matched filter output have been evaluated. Effects of A PIN diode NEP, the gain and noise figure of the EDFA, and the bandwidth of an optical filter on the packet error rate of the switching node have been compared. There is negligible error rate change depending upon the variation of the PIN diode NEP and the EDFA gain. If the bandwidth of the optical filter is below 10 times of the data rate, there is no appreciable effect on the error rate. If the noise figure of the EDFA increases, however, the power penalty increases as much as the noise figure increment at all the bit rates and for address code sets considered in this work.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제32권6A호
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• pp.558-564
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• 2007

3G Long Term Evolution, which aims for various mobile multimedia service provision by enhanced wireless interface, proposes VoIP-based voice service through a Packet Switching (PS) domain. As delay and loss-sensitive VoIP traffic flows through the PS domain, more challenging technical difficulties are expected than in Circuit Switching (CS) domain based VoIP services. Moreover, since 3G LTE, which adopts the OFDM as its physical layer, introduces Physical Resource Block (PRB) as a unit for transmission resources, new types of resource management schemes are needed. This paper proposes a PRB scheduling algorithm of MAC layer for VoIP service in 3G LTE and shows the simulation results. The proposed algorithm has two key parts; dynamic activation of VoIP priority mode to satisfy VoIP QoS requirements and adaptive adjustment of the priority mode duration in order to minimize the degradation of resource utilization.

• The Transactions of the Korean Institute of Power Electronics
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• 제12권2호
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• pp.115-122
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• 2007

In this paper, a novel fault detection method for fault tolerant control is proposed when the NPC inverter has a open failure in the switching device. The open fault of switching device is detected by checking the variation of a leg-voltage in the neutral-point-clamped inverter and the two phases control method is used for continuously balance the three phases voltage to the load. It can be achieve the fault tolerant control for improving the reliability of the NPC inverter by the fault detection and reconfiguration. This method has fast detection ability and a simple realization for fault detection, compared with a conventional method. Also, this fast detection ability improved the harmful effects such as DC-link voltage unbalance and overstress to other switching devices from a delay of fault detection. The proposed method has been verified by simulation and experiment.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• 제14권4호
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• pp.219-225
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• 2014

The New efficient Mux-based scan latch cell design and scan test of LOS/LOC modes are proposed for detection of delay faults in digital logic circuits. The proposed scan cell design can support LOS(Launch-off-Shift) and LOC(Launch-off-Capture) tests with high fault coverage and low scan power and it can alleviate the problem of the slow selector enable signal and hold signal by supporting the logic capable of switching at the operational clock speeds. Also, it efficiently controls the power dissipation of the scan cell design during scan testing. Functional operation and timing simulation waveform for proposed scan hold cell design shows improvement in at-speed test timing in both test modes.