• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.12
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• pp.1073-1077
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• 2006

Proton irradiation technology was used for improvement of switching characteristics of the PT-IGBT. Proton irradiation was carried out at 5.56 MeV energy with $1{\times}10^{12}/cm^2$ doze from the back side of the wafer. The I-V, breakdown voltage, and turn-off delay time of the device were analyzed and compared with those of un-irradiated device and e-beam irradiated device which was conventional method for minority carrier lifetime reduction. For proton irradiated device, the breakdown voltage and the on-state voltage were 733 V and 1.85 V which were originally 749 V and 1.25 V, respectively. The turn-off time has been reduced to 170 ns, which was originally $6{\mu}s$ for the un-irradiated device. The proton irradiated device was superior to e-beam irradiated device for the breakdown voltage and the on-state voltage which were 698 V and 1.95 V, respectively, nevertheless turn-off time of proton irradiated device was reduced to about 60 % compared to that of the e-beam irradiated device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.9-16
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• 2004

The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The algorithm minimizes the dependencies between groups of state variables are minimized and reduces switching activity by grouping the states depending on the state transition probability. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on the state variables. Experiment shows significant improvement in testabilities and Power dissipation for benchmark circuits.

• Journal of electromagnetic engineering and science
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• v.11 no.4
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• pp.239-249
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• 2011

In this paper, we propose a reliable $8{\times}8$ up-down switching polar relay code based on 3GPP LTE standard, motivated by 3GPP LTE down link, which is 30 bps/Hz for $8{\times}8$ MIMO antennas, and by Arikan's channel polarization for the frequency selective fading (FSF) channels with the generator matrix $Q_8$. In this scheme, a polar encoder and OFDM modulator are implemented sequentially at both the source node and relay nodes, the time reversion and complex conjugation operations are separately implemented at each relay node, and the successive interference cancellation (SIC) decoder, together with the cyclic prefix (CP) removal, is performed at the destination node. Use of the scheme shows that decoding at the relay without any delay is not required, which results in a lower complexity. The numerical result shows that the system coded by polar codes has better performance than currently used designs.

• Journal of Information Processing Systems
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• v.7 no.4
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• pp.679-690
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• 2011

In this paper we consider a local area network (LAN) of dual mode service where one is a token bus and the other is a carrier sense multiple access with a collision detection (CSMA/CD) bus. The objective of the paper is to find the overall cell/packet dropping probability of a dual mode LAN for finite length queue M/G/1(m) traffic. Here, the offered traffic of the LAN is taken to be the equivalent carried traffic of a one-millisecond delay. The concept of a tabular solution for two-dimensional Poisson's traffic of circuit switching is adapted here to find the cell dropping probability of the dual mode packet service. Although the work is done for the traffic of similar bandwidth, it can be extended for the case of a dissimilar bandwidth of a circuit switched network.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.35-42
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• 2005

This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.25-35
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• 1998

The control system architecture in switching systems have undergone numerous changes to provide various call processing capability needed in telecommunication services. During call processing in a distributed switching control environment, the delay effect due to communication among main processors or peripheral controllers is one of the limiting factors which affect the system performance. In this paper, we propose a performance model for an IPC(Inter Processor Communication) interface hardware block which is required on the ATM cell-based message processing in a distributed ATM exchange system, and analyze the primary causes which affect the processor performance through the simulation. Consequently, It can be shown that the local CPU of the several components(resources) related to the IPC scheme is a bottleneck factor in achieving the maximum system performance from the simulation results, such as the utilization of each processing component according to the change of the input message rate, and the queue length and processing delay according to input message rate. And we also give some useful results such as the maximum message processing capacity according to the change of the performance of local CPU, and the local CPU maximum throughput according to the change of average message length, which is applicable as a reference data for the improvement or expansion of the ATM control system.

• Journal of Electrical Engineering and Technology
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• v.12 no.5
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• pp.1891-1901
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• 2017

In this paper, optimal control of the fuel cell and design of a high-efficiency power converter is implemented to build a high-priced fuel cell system with minimum capacity. Conventional power converter devices use a non-isolated boost converter for high efficiency while the battery is charged, and reduce its conduction loss by using MOSFETs instead of diodes. However, the efficiency of the boost converter decreases, since overshoot occurs because there is a moment when the body diode of the MOSFET is conducted during the dead time and huge loss occurs when the dead time for the maximum-power-flowing state is used in the low-power-flowing state. The method proposed in this paper is to adjust the dead time of boost and rectifier switches by predicting the power flow to meet the maximum efficiency in every load condition. After analyzing parasite components, the stability and efficiency of the high-efficiency boost converter is improved by predictive compensation of the delay component of each part, and it is proven by simulation and experience. The variation in switching delay times of each switch of the full-bridge converter is compensated by falling time compensation, a control method of PWM, and it is also proven by simulation and experience.

• Journal of Advanced Marine Engineering and Technology
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• v.22 no.6
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• pp.901-907
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• 1998

This paper presents a real-time control technique for the development of a ship main engine remote control system, In general several tasks are executed by the event-driven method in real-time system. However when some tasks have time delay components it is difficult to achieve good real-time performance. To cope with this problem a number of timers in most conventional system have been used. In this paper we introduce a real-time control methodology of dealing effectively with tasks including time delay components using one hardware timer. And also a speed control method of main engine which includes critical revolution range a crash astern and a emergency ahead function a switching method of remote control position and a flickering method for the indication of multi-stage alarm are discussed. As long as functions and method are imple-mented as forms of tasks the development of main engine remote control systems can be easy for different types of engines.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.48-55
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• 1997

Advances in VLSI technology have brought us completely new design principles for the high-performance switching fabrics including ATM switches. From a practical point of view, port scalability of ATM switches emerges as an important issue while complexity and performance of the switches have been major issues in the switch design. In this paper, we propose a cost-effective approach to modular ATM switch design which provides the good scalability. Taking advantages of both time-division and space-division switch architectures, we propose a practically implementable large scale ATM switch architecture. We present a scalable shared buffer type switch for a building block and its expansion method. In our design, a large scale ATM switch is realized by interconnecting the proposed shared buffer switches in three stages. We also present an efficient control mechanism of the shared buffers, synchronization method for the switches in each stage, and a flow control between stages. It is believed that the proposed approach will have a significant impact on both improving the ATM switch performance and enhancing the scalability of the switch with a new cost-effective scheme for handling the traffic congestion. We show that the proposed ATM switch provides an excellent performance and that its cell delay characteristic is comparable to output queueing which provides the best performance in cell delay among known approaches.