• The Transactions of the Korea Information Processing Society
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• v.1 no.3
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• pp.367-379
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• 1994

This paper describes scheduling algorithms of the UNIX operating system and shows an analytical approach to approximate the average conditional response time for a process in the UNIX operating system. The average conditional response time is the average time between the submittal of a process requiring a certain amount of the CPU time and the completion of the process. The process scheduling algorithms in thr UNIX system are based on the priority service disciplines. That is, the behavior of a process is governed by the UNIX process schuduling algorithms that (ⅰ) the time-shared computer usage is obtained by allotting each request a quantum until it completes its required CPU time, (ⅱ) the nonpreemptive switching in system mode and the preemptive switching in user mode are applied to determine the quantum, (ⅲ) the first-come-first-serve discipline is applied within the same priority level, and (ⅳ) after completing an allotted quantum the process is placed at the end of either the runnable queue corresponding to its priority or the disk queue where it sleeps. These process scheduling algorithms create the round-robin effect in user mode. Using the round-robin effect and the preemptive switching, we approximate a process delay in user mode. Using the nonpreemptive switching, we approximate a process delay in system mode. We also consider a process delay due to the disk input and output operations. The average conditional response time is then obtained by approximating the total process delay. The results show an excellent response time for the processes requiring system time at the expense of the processes requiring user time.

• Journal of KIISE:Information Networking
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• v.29 no.1
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• pp.24-30
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• 2002

Label switching technology is currently emerging as a solution for the rapidly growing of Internet traffic demand. Multiprotocol label switching(MPLS) is one of the standards made by the Internet Engineering Task Force(IETE) intended to enhance speed, scalability, and inter-opearability between label switching technologies. In MPLS, utilization of label space is a very important factor of network performance because labels are basic unit in packet switching. We propose a algorithm to effectively use label space by a multiple disconnect timer at the label switching router. Our algorithm is based on multiple utilization of the connection release timer over the MPLS network with multiple domains. In our algorithm, a relatively linger timeout interval is assigned to the traffic with higher class by the aid of the packet classifier. This reduces delay for making a new connection and also reduces the amount of packets which will be routed to the layer 3. Simulation results shows that reduction of required label number in MPLS network and this indicate our algorithm offers better performance than the existing ones in term of utilization of label space.

• Korean Journal of Optics and Photonics
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• v.16 no.3
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• pp.287-294
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• 2005

In this paper, an optical true time-delay (TTD) for two-dimensional (2-D) phased array antennas (PAAs), composed of a multi-wavelength optical source and a fiber optic delay line matrix consisting of $2\times2$ optical switches with optical fiber connected between cross ports, has been proposed. A 2-bit $\times4-bit$ optical TTD for 10-GHz 2-D PAAs has been implemented by cascading a wavelength dependent TTD (WD-TTD) and a wavelength independent TTD (WI-TTD). The unit time delay for WD-TTD and WI-TTD have been chosen as ${\Delta}T=12ps$ and $\Delta\tau=6ps$, respectively. Time delay have been measured at all radiation angles. The maximum delay error for WD-TTD was measured to be 3 ps due to jitter incurred from gain switching. For the case of WI-TTD, error was within ${\pm}\;1\;ps$. The proposed optical TTD for a 2-D PAA has the following advantages: 1) higher gain compared to one-dimensional linear PAAs, 2) stabilization of optical power and wavelength by using a multi-wavelength optical source, and 3) fast beam scan and simple operation due to electronic control of the $2\times2$ optical switches matrix on a column-by-column basis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.445-453
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• 2002

We propose a cell-multiplexing scheme for the real-time communication service in ATM network and a new service discipline guarantee end-to-end delay based on pseudo-isochronous cell switching. The proposed scheme consists of two level frame hierarchy, upper and lower frame, which is used to assign the bandwidth and to guarantee the requested delay bound, respectively. Since the proposed algorithm employs two level frame hierarchy, it can overcome the coupling problem which is inherent to the framing strategy. The proposed scheme consists of two components, traffic controller and scheduller, as the imput traffic description model and regulates the input traffic specification. The function of the traffic controller is to shape real-time traffic to have the same input pattern at every switch along the path. The end-to-end delay is bounded by the scheduller which can limit the delay variation without using per-session jitter controllers, and therefore it can decrease the required buffer size. The proposed algorithm can support the QoS's of non-real time traffic as well as those of real time traffic

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2263-2268
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• 2015

This paper describes packet scheduling techniques that can be used to alleviate the impact of interference. The mechanism is consisted of interference estimation and master delay police. Proposed scheduling police is effective in reducing packet loss and delay. Another advantage worth mentioning, are the additional saving s in the transmitter power since packet are not transmitted when channel is bad. This paper gives that scheduling policy works only with data traffic since voice packets need to be sent at fixed intervals. However, if the delay variance is constant and the delay can be limited to a slot, it may be worthwhile to use DM packet for voice.

• Journal of KIISE:Information Networking
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• v.29 no.4
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• pp.405-411
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• 2002

Open interfaces in the optica] Internet have been progressed by OIF's ISI, ITU-T ASTN's CCI and IETF's GSMP extensions with optical switching. These open interfaces enable the separation between the control plane and the optical transport plane. This separation allows flexibility in the network, but it suffers more setup delay than the traditional switch-by-switch connection setup. We propose the parallel interworking model, which will reduce the connection setup delay in the open interface of optical Internet. Based on the switch controller's caching capability about networks states, the parallel interworking procedures between signaling protocol and GSMP protocol are performed in the switch controller. We simulated and evaluated our proposed parallel interworking model and the existing sequential interworking model in terms of a connection setup delay and a completion ratio. We observed that the completion ratios of the two interworking models were quite close. However the connection setup delay of parallel interworking model is improved by about 30% compared with that of the sequential interworking model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.7
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• pp.1018-1027
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• 1993

In this thesis, we evaluate the performance of the TDX-IB/ISDN Switching System ISS (ISDN Subscriber Subsystem) which is the ISDN user-network interface module. For this evaluation, performance indices are established and major performance parameters which influence message processing are extracted by studying the ISS structure and mechanism. To reflect these parameters, simulation model is developed and simulated. From the result of maximum throughput, message delay time, etc. , ISS message processing capability is evaluated and several method to enhance the system performance is proposed, by analyzing the system bottleneck element.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.2
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• pp.1-9
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• 1998

ATM was adopted as the switching and multiplexing technique for BISDN which aims at transmitting traffics with various characteristics in a unified network. To construct these ATM networks, the most important aspect is the design of the switching system with high performance and different service capabilities. In this paepr, we analyze the performance of an input and output queueing switch with preemptive priority which is considered to be most suitable for ATM networks. For the analysis of an input queue, we model each input queue as two separate virtual input queues for each priority class and we approximage them asindependent Geom/Geom/1 queues. And we model a virtual HOL queue which consists of HOL cells of all virtual input queues which have the same output address to obtain the mean service time at each virtual input queue. For the analysis of an output quque, we obtain approximately the arrival process into the output queue from the state of the virtual HOL queue. We use a Markov chain method to analyze these two models and obtain the maximum throughput of the switch and the mean queueing delay of cells. and analysis results are compared with simulation to verify that out model yields accurate results.

• Journal of the Korean Operations Research and Management Science Society
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• v.22 no.2
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• pp.139-151
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• 1997

An ATM switching system may be designed so that communications between processors of its control part can be performed via its switching network rather than a separate inter-processor communications (IPC) network. In such a system, there should be interfaces to convent IPC traffic from message format to cell format and vice versa, that is, mechanisms to perform the SAR (Segmentation And Reassembly) sublayer functions. In this paper, we concern the cell reassembly mechanism among them, mainly focussed on buffer management schemes. We consider a few alternatives to implement cell reassembly function block, namely, separated buffering, reserved buffering and shared buffering in this paper. In case of separated and reserved buffering, we employ a continuous time Markov chain for the performance evaluation of cell reassembly mechanism, judicially defining the states of the mechanism. Performance measures such as measage loss probability, mean number of message queued in buffer and average reassembly delay are obtianed in closed forms. In case of shared buffering, we compare the alternatives for implementing cell reassembly function block using simulation because it is almost impossible to analyze the mechanism of shared buffering by analytical modeling. Some illustrations are given for the performance analysis of the alternatives to implement cell reassembly function block.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.8
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• pp.1283-1291
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• 2002

In this paper, the PLL driven by the DDFS is designed on the schematic using the Q-logic cell based library and is implemented using FPGA QL32 x16B. The measurement results of the frequency synthesizer switching speed were agreement with a register. The simulated results show that the clock delay was generated after eleven clock and if input is random, It has influence on output DA converter has to be very extensive. Therefore, the DDFS used noise shaper to drive PLL by regular interval for input state. Also the bandwidth of DA converter very extensive, the simulation shows that the variation of small input control word is better than the switching speed of PLL.