• Title/Summary/Keyword: switching delay

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Local call processing delay of the control network in ATM switching system (ATM 교환시스템 제어계의 자국호 처리 지연 성능평가)

  • 여환근;송광석;노승환;기장근
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.12
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    • pp.3144-3153
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    • 1996
  • ATM switching system is made up of transport network and control newrk according to its functions. The control device, basic part of control network must be developed before developing any other functions, and control device must be stable and need high reliability. Out distributed ATM switching system consists of several ALSs that provides variable local call services, and an ACS that interconnect among several ALSs. Eech ALS has CCCP that takes charage of call and connection control functions, and ACS has an OMP that takes charge of OA&M(Operation, Administration and Maintenance) functios. In this paper, we analyzed the performance evaluation of control device that manipulate subscriber's call based on ITU-T Q.2931 standard protocol messages and Interprocessor communication messages. As a result of simulation when the number of ALS is under 22, as the call arrival rate increase the processor utilization of CCCP increase rapidly than that of OMP. When the number of ALS is incremented to 22, the processor utilization of CCCP is balanced with the of OMP, and when the number of ALS exceeds 22, the processor utiliztion of OMP increase rapidly. Also if messary processing time of OMP is 1.35 times that of CCCP, processor utilizations of CCCP and OMP is equal.

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Joint Blind Parameter Estimation of Non-cooperative High-Order Modulated PCMA Signals

  • Guo, Yiming;Peng, Hua;Fu, Jun
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.10
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    • pp.4873-4888
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    • 2018
  • A joint blind parameter estimation algorithm based on minimum channel stability function aimed at the non-cooperative high-order modulated paired carrier multiple access (PCMA) signals is proposed. The method, which uses hierarchical search to estimate time delay, amplitude and frequency offset and the estimation of phase offset, including finite ambiguity, is presented simultaneously based on the derivation of the channel stability function. In this work, the structure of hierarchical iterative processing is used to enhance the performance of the algorithm, and the improved algorithm is used to reduce complexity. Compared with existing data-aided algorithms, this algorithm does not require a priori information. Therefore, it has significant advantage in solving the problem of blind parameter estimation of non-cooperative high-order modulated PCMA signals. Simulation results show the performance of the proposed algorithm is similar to the modified Cramer-Rao bound (MCRB) when the signal-to-noise ratio is larger than 16 dB. The simulation results also verify the practicality of the proposed algorithm.

An Enhanced Dynamic Switching-based Flooding scheme in Low-Duty-Cycled WSNs with unreliable links (비신뢰성 링크를 가진 로우 듀티사이클 무선센서네트워크 환경에서 향상된 동적 스위칭 기반 플러딩 방법)

  • Nguyen, Dung T.;Le-Thi, Kim-Tuyen;Yeum, Sanggil;Kim, Dongsoo;Choo, Hyunseung
    • Annual Conference of KIPS
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    • 2015.04a
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    • pp.216-217
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    • 2015
  • Duty-cycling could efficiently prolong the life time of Wireless Sensor Networks (WSNs) by let nodes be in dormant state most of the time, and only wake up (for sending or receiving) for a very short period. Flooding is one critical operation of WSNs. Many studies have been studied to improve the delay and/or energy efficiency of flooding. In this paper, we propose a novel time slot design, and the switching decision that reduce energy consumption for the schedule-based flooding tree. Each node, if failed to receive from its parent, will look for other candidate, among its siblings to overhear the flooding packet. By accurately collect information from other siblings, each node can make the best as possible switching decision; therefore the energy efficiency of the network is improved.

The structure of ATM Switch with the Shared Buffer Memory and The Construction of Switching Network for Large Capacity ATM (대용량 ATM을 위한 공유 버퍼 메모리 스위치 구조 및 교환 망의 구성 방안)

  • 양충렬;김진태
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.1
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    • pp.80-90
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    • 1996
  • The efficienty of ATM is based on the statical multiplexing of fixed-length packets, which are called cells. The most important technical point for realizing ATM switching network is an arrangement of the buffers and switches. Current most ATM switching networks are being achieved by using the switching modules based on the unit switch of $8{\times}8$ 150Mb/s or $16{\times}16$ 150Mb/s, the unit switch of $32{\times}32$150Mb/s for a large scale system is under study in many countries. In this paper, we proposed a new $32{\times}32$(4.9Gb/s throughput) ATM switch using Shared buffer memory switch which provides superior traffic characteristics in the cell loss, delay and throughput performance and easy LSI(Large Scale Integrated circuit). We analytically estimated and simulated by computer the buffer size into it. We also proposed the configuration of the large capacity ATM switching network($M{\times}M$.M>1,000) consisting of multistage to improve the link speed by non-blocking.

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Intelligent Phase Plane Switching Control of Pneumatic Artificial Muscle Manipulators with Magneto-Rheological Brake

  • Thanh, Tu Diep Cong;Ahn, Kyoung-Kwan
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.1983-1989
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    • 2005
  • Industrial robots are powerful, extremely accurate multi-jointed systems, but they are heavy and highly rigid because of their mechanical structure and motorization. Therefore, sharing the robot working space with its environment is problematic. A novel pneumatic artificial muscle actuator (PAM actuator) has been regarded during the recent decades as an interesting alternative to hydraulic and electric actuators. Its main advantages are high strength and high power/weight ratio, low cost, compactness, ease of maintenance, cleanliness, readily available and cheap power source, inherent safety and mobility assistance to humans performing tasks. The PAM is undoubtedly the most promising artificial muscle for the actuation of new types of industrial robots such as Rubber Actuator and PAM manipulators. However, some limitations still exist, such as the air compressibility and the lack of damping ability of the actuator bring the dynamic delay of the pressure response and cause the oscillatory motion. In addition, the nonlinearities in the PAM manipulator still limit the controllability. Therefore, it is not easy to realize motion with high accuracy and high speed and with respect to various external inertia loads in order to realize a human-friendly therapy robot To overcome these problems a novel controller, which harmonizes a phase plane switching control method with conventional PID controller and the adaptabilities of neural network, is newly proposed. In order to realize satisfactory control performance a variable damper - Magneto-Rheological Brake (MRB) is equipped to the joint of the manipulator. Superb mixture of conventional PID controller and a phase plane switching control using neural network brings us a novel controller. This proposed controller is appropriate for a kind of plants with nonlinearity uncertainties and disturbances. The experiments were carried out in practical PAM manipulator and the effectiveness of the proposed control algorithm was demonstrated through experiments, which had proved that the stability of the manipulator can be improved greatly in a high gain control by using MRB with phase plane switching control using neural network and without regard for the changes of external inertia loads.

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Low-Latency Programmable Look-Up Table Routing Engine for Parallel Computers (병렬 컴퓨터를 위한 저지연 프로그램형 조견표 경로지정 엔진)

  • Chang, Nae-Hyuck
    • Journal of KIISE:Computing Practices and Letters
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    • v.6 no.2
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    • pp.244-253
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    • 2000
  • Since no single routing-switching combination performs the best under various different types of applications, a flexible network is required to support a range of polices. This paper introduces an implementation of a look-up table routing engine offering flexible routing and switching polices without performance degradation unlike those based on microprocessors. By deciding contents of look-up tables, the engine can implement wormhole routing, virtual cut-through routing, and packet switching, as well as hybrid switching, under a variety of routing algorithms. Since the routing engine has a piplelined look-up table architecture, the routing delay is as small as one flit, and thus it can overlap multiple routing actions without performance degradation in comparison with hardwired routers dedicated to a specific policy. Because four pipeline stages do not induce a hazard, expensive forwarding logic is not required. The routing engine can accommodate four physical links with a time shared cut-through bus or single link with a cross-bar switch. It is implemented using Xilinx 4000 series FPGA.

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Design and Performance Analysis of ISDN Switching Systems for Frame Relay Service (프레임 릴레이 서비스를 위한 ISDN 교환시스템의 설계 및 성능 분석)

  • Jang, Jae-Deuk;Kim, Jin-Tae
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.3
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    • pp.501-511
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    • 1996
  • Typical integrated service digital network(ISDN) switching systems have several shortcomings including cumulated long call set-up delay and difficulty in higher speed packet communication. The problems come from the nature of X.25 packet swiching technique used in the systems. In this thesis, to solve the above problems, the use of frame relay service within the TDX-10 ISDN switching system is proposed and a frame handling susbsystem(FHS) is designed in order to support the high speed frame relay service in the TDX-10 switching systems. In the proposed TDX-10 architecture, the 64 Kbps packet communication can be executed more ef- ficiently and high speed packet communication is allowed. To measure theperformance characteristics of the proposed systemand to compare the performance with that of the proposed system is superior to that of the existion system and to compare the performance with that of the proposed system is superior to that of the existing system. The proposed switching system offers a seamless evolutionalry path from Narrowband-ISDNto Broadband-ISDNsince itallows anefficient channelutilization and speed packet communication.

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Flow-Based Admission Control Algorithm in the DiffServ-Aware ATM-Based MPLS Network

  • Lee, Gyu-Myoung;Choi, Jun-Kyun;Choi, Mun-Kee;Lee, Man-Seop;Jong, Sang-Gug
    • ETRI Journal
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    • v.24 no.1
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    • pp.43-55
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    • 2002
  • This paper proposes a flow-based admission control algorithm through an Asynchronous Transfer Mode (ATM) based Multi-Protocol Label Switching (MPLS) network for multiple service class environments of Integrated Service (IntServ) and Differentiated Service (DiffServ). We propose the Integrated Packet Scheduler to accommodate IntServ and Best Effort traffic through the DiffServ-aware MPLS core network. The numerical results of the proposed algorithm achieve reliable delay-bounded Quality of Service (QoS) performance and reduce the blocking probability of high priority service in the DiffServ model. We show the performance behaviors of IntServ traffic negotiated by end users when their packets are delivered through the DiffServ-aware MPLS core network. We also show that ATM shortcut connections are well tuned with guaranteed QoS service. We validate the proposed method by numerical analysis of its performance in such areas as throughput, end-to-end delay and path utilization.

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A Study on Low Power Force-Directed scheduling for Optimal module selection Architecture Synthesis (최적 모듈 선택 아키텍쳐 합성을 위한 저전력 Force-Directed 스케쥴링에 관한 연구)

  • Choi Ji-young;Kim Hi-seok
    • Proceedings of the IEEK Conference
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    • 2004.06b
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    • pp.459-462
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    • 2004
  • In this paper, we present a reducing power consumption of a scheduling for module selection under the time constraint. A a reducing power consumption of a scheduling for module selection under the time constraint execute scheduling and allocation for considering the switching activity. The focus scheduling of this phase adopt Force-Directed Scheduling for low power to existed Force-Directed Scheduling. and it constructs the module selection RT library by in account consideration the mutual correlation of parameters in which the power and the area and delay. when it is, in this paper we formulate the module selection method as a multi-objective optimization and propose a branch and bound approach to explore the large design space of module selection. Therefore, the optimal module selection method proposed to consider power, area, delay parameter at the same time. The comparison experiment analyzed a point of difference between the existed FDS algorithm and a new FDS_RPC algorithm.

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Variable structure controller design for process with time delay

  • Park, Gwi-Tae;Kim, Seok-Jin;Lee, Kee-sang;Song, Myung-Hyun;Kuo, Chun-Ping;Kim, Sung-Ho
    • 제어로봇시스템학회:학술대회논문집
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    • 1993.10b
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    • pp.406-411
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    • 1993
  • A variable structure control scheme that can be applied to the process with input/output delays are proposed and its control performances are evaluated. The proposed VSCS, which is an output fedback scheme, comprises an integrator for tracking the setpoint and the Smith predictor for compensating the effects of time delay. With The VSCS, the robustness against the parameter variations and external disturbances can be achieved even when the controlled process includes I/O delays. And the desired transient response is obtained by simple adjustment of the coefficients of the switching surface equation.

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