• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.3
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• pp.45-53
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• 2019

Moving image sharing technology has developed various servers and programs for personal broadcasting. In this paper, we propose the method of transmitting the multiple moving image, including the output channel of external streaming server. It also implements and tests multiple real-time broadcast channel automatic transmission systems that assign multiple output channels to automatic output channels. As a result of the experiment, it is easy to allocate moving image to broadcast channels that are output through the external streaming server's output channels regardless of the size of the streaming server, enabling the management of efficient output channels at the time of transmission of multiple moving image. The moving image can be provided through streaming method regardless of the type of moving image from the moving image provider terminal, and the moving image transmission can be controlled in various ways, including adding and changing channels for which the moving image is sent, and sending delayed to the moving image.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.131-131
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.39-46
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• 2009

A fast-switching current-pulse driver for light emitting diode (LED) backlight is proposed. It uses a regulated drain current mirror (RD-CM) [1] and a high-voltage NMOS transistor (HV-NMOS). It achieves the fast-response current-pulse switching by using a dynamic gain-boosting amplifier (DGB-AMP). The DGB-AMP does not discharge the large HV-NMOS gate capacitance of the RD-CM when the output current switch turns off. Therefore, it does not need to charge the HV-NMOS gate capacitance when the switch turns on. The proposed current-pulse driver achieves the fast current switching by removing the repetitive gate discharging and charging. Simulation results were verified with measurements performed on a fabricated chip using a 5V/40V 0.5um BCD process. It reduces the switching delay to 360ns from 700ns of the conventional current-pulse driver.

• Journal of Power Electronics
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• v.16 no.1
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• pp.227-237
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• 2016

A novel digital current control strategy for digitally controlled DC-DC switching converters, referred to as Adjacent Cycle Sampling (ACS), is proposed in this paper. For the ACS current control strategy, the available time interval from sampling the current to updating the duty ratio, is approximately one switching cycle. In addition, it is independent of the duty ratio. As a result, the contradiction between the processing speed of the hardware and the transient response speed can be effectively relaxed by using the ACS current control strategy. For digitally controlled buck DC-DC switching converters with trailing-edge modulation, digital current control algorithms with the ACS control strategy are derived for three different control objectives. These objectives are the valley, average, and peak inductor currents. In addition, the sub-harmonic oscillations of the above current control algorithms are analyzed and eliminated by using the digital slope compensation (DSC) method. Experimental results based on a FPGA are given, which verify the theoretical analysis results very well. It can be concluded that the ACS control has a faster transient response speed than the time delay control, and that its requirements for hardware processing speed can be reduced when compared with the deadbeat control. Therefore, it promises to be one of the key technologies for high-frequency DC-DC switching converters.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.1
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• pp.195-215
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• 2021

Multipath Transport Control Protocol (MPTCP) is a transport layer protocol that enables multiple TCP connections across various paths. Due to path heterogeneity, it incurs more energy in a multipath wireless network. Recent work presents a set of approaches described in the literature to support systems for energy consumption in terms of their performance, objectives and address issues based on their design goals. The existing solutions mainly focused on the primary system model but did not discourse the overall system performance. Therefore, this paper capitalized a novel stochastically multipath scheduling scheme for data and path capacity variations. The scheduling problem formulated over MPTCP as a stochastic optimization, whose objective is to maximize the average throughput, avoid network congestion, and makes the system more stable with greater energy efficiency. To design an online algorithm that solves the formulated problem over the time slots by considering its mindrift-plus penalty form. The proposed solution was examined under extensive simulations to evaluate the anticipated stochastic optimized MPTCP (so-MPTCP) outcome and compared it with the base MPTCP and the energy-efficient MPTCP (eMPTCP) protocols. Simulation results justify the proposed algorithm's credibility by achieving remarkable improvements, higher throughput, reduced energy costs, and lower-end to end delay.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.91-102
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• 1996

The multicast routing algorithm is necessary to transmit multimedia traffic efficiently in ATM (asynchronous transfer mode) networks. In this paper, we propose the multicast routing algorithm which is based on VP/VC characteristic. The proposed algorithm is based on VP tree concept and using cost function which is based on VP/VC switching. The cost funication is composed of link cost, delay and weighting factor on delay and the weighting factor is calculated by delay sensitivity of the traffic. The proposed algorithm can choose delay bounded path which satisfies delay constraint, moreover it can choose optimal path among VPs which has the same link cost and satisfying delay constraint. With controlling weighting factor, proposed algorithm can set-up efficient path. When the weighting factor sets to be between 0.8 and 1, experimental results show that the perforance of proposed scheme is approximated to that of cost optimal algorithm and strongly delay optimized algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.236-247
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• 2002

We propose a cell－multiplexing scheme for the real－time communication service in ATM network and a new service discipline guarantee end-to-end delay based on pseudo-isochronous cell switching. The proposed scheme consists of two level frame hierarchy, upper and lower frame, which is used to assign the bandwidth and to guarantee the requested delay bound, respectively. Since the Proposed algorithm employs two level frame hierarchy, it can overcome the coupling problem which is inherent to the framing strategy It can be comparatively reduce the complexity, and still guarantee the diverse delay bounds of end-to-end. Besides, it consists of two components, traffic controller and scheduller, as the imput traffic description model and regulates the input traffic specification. The function of the traffic controller is to shape real -time traffic to have the same input pattern at every switch along the path. The end-to-end delay is bounded by the scheduller which can limit the delay variation without using per-session jitter controllers, and therefore it can decrease the required buffer size. The proposed algorithm can support the QoS's of non-real time traffic as well as those of real time traffic.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.947-960
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• 1996

The primary goal for developing high performance ATM switching systems is to minimized the probability of cell loss, cell delay and deterioration of throughput. ATM switching element that is the most suitable for this purpose is the shared buffer memory switch executed by common random access memory and control logic. Since it is difficult to manufacture VLIS(Very Large Scale Integrated circuit) as the number of input ports increased, the used of switching module method the realizes 32$\times$32, 150 Mb/s switch utilizing 8$\times$8, 600Mb/s os 16$\times$16, 150Mb/s unit switch is latest ATM switching technology for small and large scale. In this paper, buffer capacity satisfying total-memory-reduction effect by buffer sharing in a shared buffer memory switch are analytically evalu ated and simulated by computer with cell loss level at traffic conditions, and also features of switching network utilizing the switching module methods in small and large-capacity ATM switching system is analized. Based on this results, the structure in outline of 32$\times$32(4.9Gb/s throughput), 150Mb/s switches under research in many countries is proposed, and eventually, switching-network structure for ATM switching system of small and large and capacity satisfying with above primary goals is suggested.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1947-1949
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• 1999

Carrier lifetime in silicon power devices caused switching delay and excessive power loss at high frequency switching. We studied transient turn-on/turn-off transient characteristics of electron irradiated and proton irradiated silicon pn junction diodes. Both the electron and proton irradiation of power devices have already become a widely used practice to reduce minority carrier lifetime locally[1]. The sample is n+p junction diode, made by ion implantation on a $20\Omega.cm$ p-type wafer. We investigated turn-on/turn-off transient & breakdown voltage characteristics by digital oscilloscope. Our data show that proton irradiated samples show better performance than electron irradiated samples.

• The Transactions of the Korea Information Processing Society
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• v.7 no.6
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• pp.1941-1948
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• 2000

Multistage interconnection networks (MINs) have been recognized as an efficient interconnection network for high-performance computer systems and also have been recently identified to be effective for a switching fabric of new communication structures - gigabit ethernet switch, terabit router, and ATM (asynchronous transfer mode). While lots of models analyzing the performance of MINs have been proposed, they are either inaccurate or, even if accurate, very complex for the analysis. In this paper, we propose an extremely simple mode for evaluating the multibuffered MIN with small clock cycles based on the approximation approach. Comprehensive computer simulation shows that the proposed model is very accurate in terms of the throughput and mean delay. Furthermore, it significantly reduces the computing overhead due to its simplicity.