• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.4
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• pp.225-233
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• 2010

In this paper, we try to improve the performance of the demand paging loader suggested to use the demand paging way that is not based on operating system. The demand paging switching strategy used in the existing operating system can know the recently used pages by running multi-processing. Then, based on it, some page switching strategies have been made for the recently used pages or the frequently demanded pages. However, the strategies based on operating system cannot be applied in single processing that is not based on operating system because any context switching never occur on the single processing. So, this paper is trying to suggest the demand paging switching strategies that can be applied in paging loader running in single process. In the Return-Prediction-Algorithm, we saw the improved performance in the program that the function call occurred frequently in a long distance. And then, in the Most-Frequently-Used-Page-Remain-Algorithm, we saw the improved performance in the program that the references frequently occurred for the particular pages. Likewise, it had an enormous effect on keeping the memory reduction performance by the demand paging and reducing the running time delay at the same time.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.1
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• pp.41-60
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• 2018

Recently, road traffic congestion is becoming a serious urban phenomenon, leading to massive adverse impacts on the ecology and economy. Therefore, solving this problem has drawn public attention throughout the world. One new promising solution is to take full advantage of vehicular ad hoc networks (VANETs). In this study, we propose a new traffic congestion detection and quantification method based on vehicle clustering and fuzzy assessment in VANET environment. To enhance real-time performance, this method collects traffic information by vehicle clustering. The average speed, road density, and average stop delay are selected as the characteristic parameters for traffic state identification. We use a comprehensive fuzzy assessment based on the three indicators to determine the road congestion condition. Simulation results show that the proposed method can precisely reflect the road condition and is more accurate and stable compared to existing algorithms.

• Journal of the Semiconductor & Display Technology
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• v.5 no.4 s.17
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• pp.1-4
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• 2006

Recently, with rapid development of digital media like semiconductor and large flat panel display, the manufacturing equipment is required to have high precision over large travel range. Moreover it should have high product throughput. To achieve high product throughput, a controller should perform fast point-to-point motion and high precision positioning after settling in spite of external disturbances or residual vibrations. We proposed a new mode switching control algorithm with an application to dual stage for long range and high precision positioning. The proposed algorithm uses a proximate time-optimal servomechanism for the fast settling and a time-delay controller for the high precision positioning. Experimental results show that the proposed method enables smooth mode switching and improves the settling time and the precision accuracy after settling by over than 33% and 45%, respectively.

• Korean Management Science Review
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• v.10 no.1
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• pp.139-156
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• 1993

Various ATM switches have been proposed since Asynchronous Transfer Mode (ATM) was recognized as appropriate for implementing broadband integrated services digital network (BISDN). An ATM switching network may be evaluated on two sides : traffic performances (maximum throughput, delay, and packet loss probability, etc.) and structural features (complexity, i.e. the number of switch elements necessary to construct the same size switching network, maintenance, modularity, and fault tolerance, etc.). ATM switching networks proposed to date tend to show the contrary characteristics between structural features and traffic performance. The Knockout Switch, which is well known as one of ATM switches, shows a good traffic performance but it needs so many switch elements and buffers. In this paper, we propose an input and output buffered Knockout Switch for the purpose of reducing the number of switch elements and buffers of the existing Knockout Switch. We analyze the traffic performance and the structural features of the proposed switching architecture through a discrete time Markov chain and compare with those of the existing Knockout Switch. It was found that the proposed architecture could reduce more than 40 percent of switch elements and more than 30 percent of buffers under a given requirement of cell loss probability of the switch.

• Journal of Power Electronics
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• v.19 no.4
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• pp.1034-1044
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• 2019

In medium-voltage and high-voltage high-power converters, the switching devices need to operate at a low switching frequency to reduce power loss and increase the power capacity. This increases the delay of the signal sampling and PWM. It also makes the cross-couplings of the d-q current components more severe. In addition, the LCL filter has three cross-coupling loops and is prone to resonance. In order to solve these problems, this paper establishes a complex vector model of an LCL type grid-connected converter. Based on this model, two multiple decoupling current control strategies with passive damping / notch damping are proposed for the LCL type grid-connected converter. The proposed strategies can effectively eliminate the cross-couplings of the converter, achieve independent control of the d-q current components, expand the stable region and suppress the resonance of the LCL filter. Simulation and experimental results verify the correctness of the theoretical analysis and the feasibility of the proposed strategies.

• Fire Science and Engineering
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• v.19 no.2 s.58
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• pp.75-80
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• 2005

This dissertation is about the development of PTC(Positive Temperature Coefficient) thermistor by composition method. A multilayer-type PTC samples were fabricated under optimal conditions after setting the experimental composition equation as $(0.90Ba+0.05Sr+0.05Ca)TiO_3+0.01TiO_3+0.01SiO_2+0.0008MnO_2+0.0018Nb_2O_5$ and their testing results were analyzed. The fabrication method of SMD(Surface Mounted Device) multilayer -type sample based on the composition ratio has the advantages in lowering its resistivity at room temperature, considerably, and increasing maximum current level, as needed. Although there is a disadvantage of peak resistivity drop by the multilayer, causing the increasement of thermal capacity. and thereby, increasing the switching delay time, a high applying voltage can increase the peak resistivity and shorten the switching delay time. The voltage-current characteristic showed that the more multilayers increased the initial maximum current and the transition voltage that increased the resistivity abruptly according to the curie point. The element it could be applied with the sensor for the fire detector.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.9-15
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• 2006

This paper shows the impedance profile of PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks) including core and I/O circuit. Through the simulated results, we find that the core power noise having connection with I/O power is affected by I/O switching. Also, using designed $74{\times}5inch$ DLL(Delay Locked Loop) test board, we analyzed the effect of power noise on operation region of chip. Jitter of a DLL measure for frequency of $50{\sim}400MHz$ and compared with impedance obtained result of simulation. Jitter of a DLL are increased near about frequency of 100MHz. It is reason that the resonant peak of PDNs has an impedance of more the 1ohm on 100MHz. we present the impedance profile of a chip and board for the decoupling capacitor reduced the target impedance. Therefore, power supply network design should be considered not only decoupling capacitors but also core switching current and I/O switching current.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.17-25
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• 2016

This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a $4{\times}4$ multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.10
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• pp.40-50
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• 1999

The novel network architecture is recently required to accommodate a variety and intelligence of communication services. It is also required to provide customized network functions and to efficiently satisfy a various user's requirements. Accordingly, open network architecture based on ATM transport network features has been mainly studied in communication network. This paper evaluates the VSN(Virtual Switch Network) characteristics in the call processing of IMT-2000 switching system, which is composed of VSN instead of ATM switch network. VSN means switch network which is composed of ATM transport network. As a result, this paper proposes new VSN based ATM-MSC architecture with integrated call and connection control systems. and evaluates call processing delay characteristics using call process procedures. Internal call processing delay is increased approximately 3.5msec than the conventional ATM switching system. The experimental values applied in the analysis condition are the load 0.8, and the 100km distance between CCCPs(Call and Connection Control Processors) and VSNs. It is confirmed that the VSN has the potentiality in the practical implementation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.131-144
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• 2015

An extensive investigation of the influence of gate engineering on the CNTFET switching, high frequency and circuit level performance has been carried out. At device level, the effects of gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. It is revealed that hetero - material - gate CNTFET(HMG - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, and is more suitable for use in low power and high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the performance parameters of circuits have been calculated and the optimum combinations of ${\Phi}_{M1}/{\Phi}_{M2}/{\Phi}_{M3}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product(PDP). We show that, compared to a traditional CNTFET - based circuit, the one based on HMG - CNTFET has a significantly better performance (SNM, energy, PDP). In addition, results also illustrate that HMG - CNTFET circuits have a consistent trend in delay, power, and PDP with respect to the transistor size, indicating that gate engineering of CNTFETs is a promising technology. Our results may be useful for designing and optimizing CNTFET devices and circuits.