• Title/Summary/Keyword: switching delay

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An Efficient Mode Selection Method for OFDM Based Multi-System Wireless Communication Systems (OFDM 기반 다중 무선 통신 환경에서의 효과적인 모드 선택 기법)

  • Park, Jong-Min;Kang, Min-Soo;Cho, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.2
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    • pp.19-25
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    • 2008
  • When there are numerous wireless communication systems co-existing in the limited available frequency resource, an unexpected time delay can be caused during the system switching. So, in order to reduce this time delay, a mode selection method is required. In this paper, we propose a mode selection method to minimize the time delay for multi-system wireless communication systems. For the sake of efficiency, the mode selection method is designed by analyzing the preamble characteristics of different standards. Instead of performing a full search, we propose the preamble partial search to reduce the time delay to a minimum. Simulated with Matlab in an additive white Gaussian noise(AWGN) environment with a signal to noise ratio(SNR) of 10dB and bit error rate(BER) of $10^{-6}$, we evaluated and showed the performance improvement gained by using our proposed mode selection method.

Performance Analysis of Threshold-based Bernoulli Priority Jump Traffic Control Scheme (동적우선권제어함수 기반 TBPJ 트래픽 제어방식의 성능분석)

  • Kim, Do-Kyu
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.11S
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    • pp.3684-3693
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    • 2000
  • In this paper, performance of a nonblocking high speed packet switch with switching capacity m which adopts a dynamic priority control function (DPCF) of a threshold- based Bernoulli priority jump (TBPJ) scheme is considered. Each input queue has two separate buffers with different sizes for two classes of traffics, delay-sensitive and loss-sensitive traffics, and adopts a TBPJ scheme that is a general state-dependent Bernoulli scheduling scheme. Under the TBP] scheme, a head packet of the delay-sensitive traffic buffer goes into the loss -sensitive traffic buffer with Hernoulli probability p according to systems states that represent the buffer thresholds and the number of packets waiting for scheduling. Performance analysis shows that TBPJ scheme obtains large performance build-up for the delay-sensitive traffic without performance degradation for the loss-sensitive traffic. In addition to, TBP] scheme shows better performance than that of HOL scheme.

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Predictive Current Control of Four-Quadrant Converters Based on Specific Sampling Method and Modified Z-Transform

  • Zhang, Gang;Qian, Jianglin;Liu, Zhigang;Tian, Zhongbei
    • Journal of Power Electronics
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    • v.19 no.1
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    • pp.179-189
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    • 2019
  • Four-quadrant converters (4QCs) are widely used as AC-DC power conversion interfaces in many areas. A control delay commonly exists in the digital implementation process of 4QCs, especially for high power 4QCs with a low switching frequency. This usually results in alternating current distortion, increased current harmonic content and system instability. In this paper, the control delay is divided into a computation delay and a PWM delay. The impact of the control delay on the performance of a 4QC is briefly analyzed. To obtain a fundamental value of AC current that is as accurately as possible, a specific sampling method considering the PWM pattern is introduced. Then a current predictive control based on a modified z-transform is proposed, which is effective in reducing the control delay and easy in terms of digital implementation. In addition, it does not depend on object models and parameters. The feasibility and effectiveness of the proposed predictive current control method is verified by simulation and experimental results.

A CMOS Hysteretic DC-DC Buck Converter with a Constant Switching Frequency

  • Jeong, Taejin;Yoon, Kwang S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.4
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    • pp.471-476
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    • 2015
  • This paper describes a CMOS hysteretic DC-DC buck converter with a constant switching frequency for mobile applications. The inherent problems of a large output ripple voltage that the conventional hysteretic DC-DC buck converters has faced have been resolved by using the proposed DC-DC buck converter which employed a ramp generator circuit to be able to increase a switching frequency. The proposed architecture enables the settling response time of charge pump circuit within the converter to become less than 6us suitable for mobile applications. The proposed DC-DC buck converter was implemented by using 0.35 um BCDMOS process and die size was $1.37mm{\times}1.37mm$. The measurement results showed that the proposed circuit received the input of 3.7 V and generated output of 1.2 V with the output ripple voltages less than 20 mV under load currents of 100~400 mA at the fixed switching frequency of 2 MHz. The maximum efficiency of the proposed hysteretic buck converter was measured to be around 93%.

Improvement of Switching Speed of a 600-V Nonpunch-Through Insulated Gate Bipolar Transistor Using Fast Neutron Irradiation

  • Baek, Ha Ni;Sun, Gwang Min;Kim, Ji suck;Hoang, Sy Minh Tuan;Jin, Mi Eun;Ahn, Sung Ho
    • Nuclear Engineering and Technology
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    • v.49 no.1
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    • pp.209-215
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    • 2017
  • Fast neutron irradiation was used to improve the switching speed of a 600-V nonpunch-through insulated gate bipolar transistor. Fast neutron irradiation was carried out at 30-MeV energy in doses of $1{\times}10^8n/cm^2$, $1{\times}10^9n/cm^2$, $1{\times}10^{10}n/cm^2$, and $1{\times}10^{11}n/cm^2$. Electrical characteristics such as current-voltage, forward on-state voltage drop, and switching speed of the device were analyzed and compared with those prior to irradiation. The on-state voltage drop of the initial devices prior to irradiation was 2.08 V, which increased to 2.10 V, 2.20 V, 2.3 V, and 2.4 V, respectively, depending on the irradiation dose. This effect arises because of the lattice defects generated by the fast neutrons. In particular, the turnoff delay time was reduced to 92 nanoseconds, 45% of that prior to irradiation, which means there is a substantial improvement in the switching speed of the device.

Design and Analsis of a high speed switching system with two priority (두개의 우선 순위를 가지는 고속 스윗칭 시스템의 설계 및 성능 분석)

  • Hong, Yo-Hun;Choe, Jin-Sik;Jeon, Mun-Seok
    • The KIPS Transactions:PartC
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    • v.8C no.6
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    • pp.793-805
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    • 2001
  • In the recent priority system, high-priority packet will be served first and low-priority packet will be served when there isn\`t any high-priority packet in the system. By the way, even high-priority packet can be blocked by HOL (Head of Line) contention in the input queueing System. Therefore, the whole switching performance can be improved by serving low-priority packet even though high-priority packet is blocked. In this paper, we study the performance of preemptive priority in an input queueing switch for high speed switch system. The analysis of this switching system is taken into account of the influence of priority scheduling and the window scheme for head-of-line contention. We derive queue length distribution, delay and maximum throughput for the switching system based on these control schemes. Because of the service dependencies between inputs, an exact analysis of this switching system is intractable. Consequently, we provide an approximate analysis based on some independence assumption and the flow conservation rule. We use an equivalent queueing system to estimate the service capability seen by each input. In case of the preemptive priority policy without considering a window scheme, we extend the approximation technique used by Chen and Guerin [1] to obtain more accurate results. Moreover, we also propose newly a window scheme that is appropriate for the preemptive priority switching system in view of implementation and operation. It can improve the total system throughput and delay performance of low priority packets. We also analyze this window scheme using an equivalent queueing system and compare the performance results with that without the window scheme. Numerical results are compared with simulations.

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Tandem Architecture for Photonic Packet Switches

  • Casoni, Maurizio;Raffaelli, Carla
    • Journal of Communications and Networks
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    • v.1 no.3
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    • pp.145-152
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    • 1999
  • A new switch architecture is presented to enhance out-put queuing in photonic packet switches. Its appkication is for a packet switching enviroment based on the optical transport of fixed length packets. This architecture consists of a couple of cas-cading switching elements with output queuing, whose buffer ca-pacity is limited by photonic technology. The introduction of a suitable buffer management allows a very good and balanced ex-ploitation of the available optical memories, realized with fiber de-lay lines. In particular, packet loss performance is here evaluated showing the improvement with respect to the single switch and a way to design large optical switches is shown in order to meet broadband network requirements.

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Design and Implementation of Driver Circuit for AC TFEL Flat Panel Display (AC TFEL 평판표시장치의 구동회로 설계 및 구현)

  • 오건창;김명식;권용무;오명환;김덕진
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.30B no.10
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    • pp.27-34
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    • 1993
  • In this paper, a driver system is designed and implemented to achieve 4-level gray scale CH TFEL(Thin Film ElectroLuminescent) flat panel display. To implement the driver system, commercial EL driver IC chips are used to apply high voltage pulses to the EL panel and a high voltage switching circuit is designed for the EL driver IC. A new method of reducing storage delay time of transistor is proposed to obtain a reliable switching circuit. The controller for EL driver and switching circuit is also designed. The designed driving scheme applicable to EL display with 4-level gray scale is based on the linear characteristics of brightness vs. frequency of AC TFEL. By experiment, it has been shown that the brightness of AC TEFL display with the implemented driving system is controlled by the level of gray scale.

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Performance Analysis of Multi-Link Switching Method with Concurrent Processing Function (병행처리 기능을 갖는 멀티링크 스위칭기법의 성능 분석)

  • 유동관
    • Journal of the Korea Society of Computer and Information
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    • v.6 no.2
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    • pp.84-89
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    • 2001
  • In this paper, an improved protocol of Multi-Link Switching Method is proposed by supplementing a concurrent processing function. This protocol is proposed to complement the shortcomings of the conventional Multi-Link Switching Method which is used for the medium access in LAN. We analyzed the improved protocol in channel utilization viewpoint and compared the result with that of the conventional protocol From this result, we showed that the channel utilization of the improved protocol is superior to that of the conventional protocol when the maximum normalized propagation delay is increased.

Hysteresis Current Control with Self-Locked Frequency Limiter for VSI Control (자기동조 주파수 제한기를 갖는 전압원 인버터의 히스테리시스 전류제어)

  • Choe, Yeon-Ho;Im, Seong-Un;Gwon, U-Hyeon
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.51 no.1
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    • pp.23-33
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    • 2002
  • A hysteresis control is widely used to control output current of inverter. A hysteresis bandwidth is affected by system parameters such as source voltage, device on/off time, load inductance and resistance. The frequency limiter is used to protect switching devices overload. In the conventional hysteresis controller, a lock-out circuit with D-latch and timer is used to device protection circuit. But switching delay time and harmonic components are appeared in output current. In this paper the performance of lock-out circuit is tested, and new circuit for switching device fault protection is proposed ad it's performance is simulated.