• Journal of Drive and Control
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• v.17 no.4
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• pp.46-53
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• 2020

In this paper, the development of a manually and continuously variable impact force control mechanism for hydraulic breakers was studied. Generally, a hydraulic breaker has one or two piston strokes. Hydraulic breakers, which have two strokes, have two valve-switching ports and make short and long piston strokes. The piston stroke valve controls the piston stroke by opening and closing a short stroke-switching port. The short piston stroke mode is used to break soft rock, concrete, or asphalt. This stroke control valve system is not popular for small hydraulic breakers mounted on 1 to 14-ton excavators. To preserve the carrier-like excavator, proper breaking force is needed, and it can be easily controlled by multiple piston stroke control valves. The easiest way to control these breakers is to use several switching ports and valves but they are not easy to install in small hydraulic breakers and are expensive. To use only one switching port and valve, a method can be used to change the open area of the switching port to delay valve switching. This method provides multiple piston strokes.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.1
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• pp.38-44
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• 1993

A model for BICMOS buffer switching operation is presented, including the influence of bipolar base transit time and collector-base capacitances. A closed-form solution for the propagation delay-time is obtained assuming low level injection and channel velocity limitation. For the high level injection case, the delay-times are numerically obtained using effective current gain. These results are compared with those by HSPICE simulation, which shows good agreement. It is noted that the collector-base capacitance strongly affects the delay-time. The effects of voltage scaling are also investigated, which shows the model can be applied for the reduced supply voltages.

• ETRI Journal
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• v.28 no.1
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• pp.31-44
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• 2006

In a packet switching network, congestion is unavoidable and affects the quality of real-time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well-known solutions for quality-of-service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.520-527
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• 2016

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.6
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• pp.744-749
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• 2013

The protection switching technology is widely adopted in the fiber-optical transmission equipments based on TDM(Time Division Multiplexing), such as PDH, SDH/SONET. A variety of protection switching algorithms for Ethernet networks and the progress of standardization are summarized in the document. There are several kinds of protection switching algorithms for Ethernet networks, such as STP, RSTP, MSTP and etc. However, since Ethernet signal move through detour route, it causes much time to recover. Accordingly, it is difficult to secure a usability of Ethernet networks and QOS(Quality of Service). Also, if the protection switching protocol standardized by IEEE and ITU-T is used, it remains a inherent network switching time for protection. Therefore, a specific protection switching algorithm for Ethernet are needed for seamless and stable operation of Ethernet networks service for Distribution Automation System(DAS). A reliable protection algorithm with no switching delay time is very important to implement Self-healing service for DAS. This study of FPGA based protection switching algorithm for Ethernet networks shows that in case of faults occurrence on distribution power network, immediate fault isolation and restoration are conducted through interaction with distribution equipments using P2P(Peer to Peer) communication for protection coordination. It is concluded that FPGA based protection switching algorithm for Ethernet networks available 0ms switching time is crucial technology to secure reliability of DAS.

• The KIPS Transactions:PartC
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• v.10C no.4
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• pp.447-454
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• 2003

Optical burst switching (OBS) has been proposed to reduce the use of fiber delay lines (FDLs) and to realize the optical switching paradigm of the next-generation ail optical networks. The OBS can provide improvements over wavelength routing in terms of bandwidth efficiency and core network scalability via statistical multiplexing of bursts. Recently, another challenging issue is how to upport quality of service (QoS) in the optical burst switching networks. In this paper, we propose a deflection routing scheme to guarantee the QoS for the OBS networks to detour lower priority burst forward to the deflection routing path when congested. A big advantage of the proposed scheme is the simplicity of QoS provision, that comes from the simple QoS provisioning algorithm. Also, the QoS provisioning scheme be able to make efficient networks by fairly traffic distributing with the reduce of the use of FDLs at core routers. The QoS provisioning scheme has been verified to reliably guarantee the QoS of priority 0, 1, 2 burst and to efficiently utilize network resources by computer simulations using OPNET As results, the end-to-end delay of high priority burst is improved, and the network efficiency is also improved.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.8
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• pp.3474-3497
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• 2016

Network Function Virtualization (NFV) and Software Defined Networking (SDN) are recently considered as very promising drivers of the evolution of existing middlebox services, which play intrinsic and fundamental roles in today's networks. To address the virtual service deployment issues that caused by introducing NFV or SDN to networks, this paper proposes an optimal solution by combining quantum genetic algorithm with cooperative game theory. Specifically, we first state the concrete content of the service deployment problem and describe the system framework based on the architecture of SDN. Second, for the service location placement sub-problem, an integer linear programming model is built, which aims at minimizing the network transport delay by selecting suitable service locations, and then a heuristic solution is designed based on the improved quantum genetic algorithm. Third, for the service amount placement sub-problem, we apply the rigorous cooperative game-theoretic approach to build the mathematical model, and implement a distributed algorithm corresponding to Nash bargaining solution. Finally, experimental results show that our proposed method can calculate automatically the optimized placement locations, which reduces 30% of the average traffic delay compared to that of the random placement scheme. Meanwhile, the service amount placement approach can achieve the performance that the average metric values of satisfaction degree and fairness index reach above 90%. And evaluation results demonstrate that our proposed mechanism has a comprehensive advantage for network application.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7B
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• pp.1034-1042
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• 2010

As many researchers have been interested in Green IT, Energy Efficient Ethernet(EEE) with rate adaptation has recently begun to receive many attention. However, the rate adaptation scheme can have different energy efficiency and delay according to the characteristics of various traffic patterns. Therefore, in this paper, we analyze the impact of different traffic patterns on the energy efficiency and delay in Ethernet with rate adaptation. To do this, firstly we design a rate adaptation simulator which consists of Poisson based traffic generator, Pareto distribution based ON-OFF generator and Ethernet node with rate adaptation by using OPNET Modeler. Using this simulator, we perform the simulation in view of the total number of switching, transmission rate reduction, energy saving ratio and average queueing delay. Simulation results show that IP traffic patterns with high self-similarity affect the number of switching, rate reduction and energy saving ratio. Additionally, the transition overhead is caused due to the high self-similar traffic.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.3
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• pp.275-284
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• 2004

This paper discusses how to control the compensation voltages in dynamic voltage restorers (DVR). On analyzing the power circuit of a DVR system, control limitations and control targets are presented for the voltage compensation in DVRs. Based on the preceded power stage analysis, a novel controller for the compensation voltages of DVRs is proposed by a feed forward control scheme. This paper discusses also the time delay problems in the control system of DVRs. Digitally controlled DVR systems normally have control delay at amount of one sampling time of the control system and a half of the switching period of the DVR inverter. The control delay in digital controllers increases the dimension of the system transfer function one degree higher, which makes the control system more complicate and more unstable. This paper proposes a guide line to design the control gain, appropriate output filter parameters and inverter switching frequency for DVRs with digital controllers. Proposed theory is verified by an experimental DVR system with a full digital controller.

• Journal of KIISE:Information Networking
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• v.31 no.2
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• pp.233-241
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• 2004

In this paper, we propose a packet-lossless fast rerouting scheme at a link/node fault in MPLS (Multiprotocol Label Switching) network with minimized accumulated buffer delay problem at ingress node. The proposed scheme uses a predefined, alternative LSP (Label Switched Path) In order to restore user traffic. We propose two restoration approaches. In the first approach, an alternative LSP is initially allocated with more bandwidth than the protected working LSP during the failure recovery phase. After the failure recovery, the excessively allocated bandwidth of the alternative LSP is readjusted to the bandwidth of the working LSP. In the second approach, we reduce the length of protected working LSP by using segment-based restoration. The proposed approaches have merits of (ⅰ) no buffer delay problem after failure recovery at ingress node, and (ⅱ) the smaller required buffer size at the ingress node than the previous approach.