• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.5
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• pp.13-18
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• 1978

A delay switching PLL (DSPLL) is proposed for improvement of the frequency acquisition Performance (pull-in range) while keeping a narrow bandwidth LPF. It has, between the phase detector and the LPF, just a simple RC delay circuit, a switch and another phase detector controlling the switching time. For the common second order PLL, the pull-in capability of the DSPLL is analyzed approximately, without considering additive white noise effect, and verified experimentally. It is shown that the delay switching extends the pull-in range significantly, as much as a half of lock-range. At the phase tracking mode, the delay switching does not function, to make the DSPLL be a normal PLL.

• Journal of Korean Institute of Industrial Engineers
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• v.28 no.2
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• pp.139-146
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• 2002

The third generation mobile communication needs to provide multimedia service with increased data rates. Thus an efficient allocation of radio and network resources is very important. This paper models the 'burst switching' as an efficient radio resource allocation scheme and the performance is compared to the circuit and packet switching. In burst switching, radio resource is allocated to a call for the duration of data bursts rather than an entire session or a single packet as in the case of circuit and packet switching. After a stream of data burst, if a packet does not arrive during timer2 value ($\tau_{2}$), the channel of physical layer is released and the call stays in suspended state. Again if a packet does not arrive for timerl value ($\tau_{1}$) in the suspended state, the upper layer is also released. Thus the two timer values to minimize the sum of access delay and queuing delay need to be determined. In this paper, we focus on the decision of $\tau_{2}$ which minimizes the access and queueing delay with the assumption that traffic arrivals follow Poison process. The simulation, however, is performed with Pareto distribution which well describes the bursty traffic. The computational results show that the delay and the packet loss probability by the burst switching is dramatically reduced compared to the packet switching.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.8
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• pp.1534-1544
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• 2002

The TDCSA(Time Delay Control with Switching Action) method, which consists of Time Delay Control(TDC) and a switching action of sliding mode control(SMC), has been proposed as a promising technique in the robust control area, where the plant has unknown dynamics with parameter variations and substantial disturbances are preset. When TDCSA is applied to the plant with saturation nonlinearity, however, the so-called windup phenomena are observed to arise, causing excessive overshoot and instability. The integral element of TDCSA and the saturation element of a plant cause the windup phenomena. There are two integral effects in TDCSA. One is the integral effect occurred by time delay estimation of TDC. Other is the integral term of an integral sliding surface. In order to solve this problem, we have proposed an anti-windup scheme method for TDCSA. The stability of the overall system has been proved for a class of nonlinear system. Experiment results show that the proposed method overcomes the windup problem of the TDCSA.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.1120-1124
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• 2005

We reviewed controllers with a time delay estimation in this paper. Time delay control (TDC) and sliding mode control (SMC) are well known robust control schemes. Basically, the TDC has a main characteristic called a time delay estimation from which we can estimate the total uncertainty of a system. . The TDC causes the stick-slip in the case of systems with a friction. The so-called TDCSA which are short for TDC with switching action was developed to reduce the stick-slip. The TDC has the additional switching action term in the TDC structure. In the other hand, the SMC dose not have a time delay estimation but instead it can estimate the system uncertainty through the switching action. The SMC has a difficulty to estimate the total uncertainty of a system because it does not have a time delay estimation. In order to solve the difficulty, some control schemes were developed. Among them, we need to focus our attention on two control schemes: SMCPE and SMCTE, which are short for sliding mode control with a perturbation estimation and sliding mode control with a time delay estimation, respectively. In this paper, we analyzed and compared the characteristic of above three controllers. Even though the motives for the development of three control schemes are different, three control schemes have much in common in terms of their controller structures.

• Journal of Communications and Networks
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• v.13 no.5
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• pp.536-543
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• 2011

The heterogeneous postal delivery model assumes that each intermediate node in the multicasting tree incurs a constant switching time for each message that is sent. We have proposed a new model where we assume a more generalized switching time at intermediate nodes. In our model, a child node v of a parent u has a switching delay vector, where the ith element of the vector indicates the switching delay incurred by u for sending the message to v after sending the message to i-1 other children of u. Given a multicast tree and switching delay vectors at each non-root node 5 in the tree, we provide an O(n$^{\frac{5}{2}}$) optimal algorithm that will decide the order in which the internal (non-leaf) nodes have to send the multicast message to its children in order to minimize the maximum end-to-end delay due to multicasting. We also show an important lower bound result that optimal multicast switching delay problem is as hard as min-max matching problem on weighted bipartite graphs and hence O(n$^{\frac{5}{2}}$) running time is tight.

• Proceedings of the KIPE Conference
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• 1998.07a
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• pp.85-89
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• 1998

A switching power stage is a very nonlinear system because it has two or more operation modes in one switching cycle. To model a switching power stage, the state space averaging method has been developed. Though it allows a unified treatment of a large variety of switching power stages, the model it yields is always very nonlinear. So, it is required to linearize the averaged model. But it is well known that a controller for a nonlinear plant designed by the linearization frequently fails in showing satisfactory control performance. Hence it is very natural to try to design a nonlinear controller for a switching power stage. In design of a switching power system, nonlinear control approaches such as adaptive control and fuzzy control have been widely studied so far. In this research, a recently developed control method, time delay control is briefly studied and a design example for a ZVS PWM half bridge converter is given. The performance of the time delay controller is compared to its conventional counterpart, PI controller by computer simulations.

• Journal of Power Electronics
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• v.11 no.2
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• pp.156-162
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• 2011

The control loop time delay caused by sampling, the zero-order-holder effect and calculations is inevitable in the digital control of dc-dc switching converters. The time delay will limit the bandwidth of the control loop and therefore degrade the transient performance of digital systems. In this paper, the quantization time delay effects with different time delay values based on a generic second-order system are analyzed. The conclusion that the bandwidth of digital control is reduced by about 20% with a one cycle delay and by 50% with two cycles of delay in comparison with no time delay is obtained. To compensate the time delay and to increase the control loop bandwidth, a duty ratio predictive control scheme based on linear extrapolation is proposed. The compensation effect and a comparison of the load variation transient response characteristics with analogy control, conventional digital control and duty ratio predictive control with different time delay values are performed on a point-of-load Buck converter by simulations and experiments. It is shown that, using the proposed technique, the control loop bandwidth can be increased by 50% for a one cycle delay and 48.2% for two cycles of delay when compared to conventional digital control. Simulations and experimental results prove the validity of the conclusion of the quantization effects of the time delay and the proposed control scheme.

• Journal of the Korean Society of Clothing and Textiles
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• v.37 no.4
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• pp.526-539
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• 2013

This study analyzed the effects of internet fashion consumer's anticipated regret and the selection difficulty on decision making delay and purchase switching intention. The survey was conducted in 2012 on internet fashion consumers in their 20s to 40s from May 1 to June 30; subsequently, 487 responses were used for the data analysis. The anticipated regret of internet fashion consumers was composed of product, service, social psychology, and function-related anticipated regret. The selection difficulty of internet fashion consumers was composed of process, information, and experience-related selection difficulty. There are significant differences in anticipated regret, selection difficulty, decision making delay, and purchase switching intention by gender. The anticipated regret (product, service, and social psychology-related anticipated regret) and selection difficulty effected decision making delay. In addition, the anticipated regret for product and selection difficulty by process or information influenced purchase switching intention. The results of this study provide useful information on the success and efficient operation of internet shopping malls.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.6
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• pp.2870-2888
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• 2017

Recent studies have shown that the flow table size of hardware SDN switch cannot match the number of concurrent flows. Combined SDN Forwarding Element (CFE), which comprises several software switches and a hardware switch, becomes an alternative approach to tackle this problem. Due to the limited capacity of software switch, the way to route concurrent flows in CFE can largely affect the maximum delay that a flow suffers at CFE. As delay-guarantee is a nontrivial task for network providers with the increasing number of delay-sensitive applications, we propose an analytical model of CFE to evaluate a rules placement solution first. Next, we formulate the problem of Rules Placement with delay guarantee in CFE (RPCFE), and present the genetic-based rules placement (GARP) algorithm to solve the RPCFE problem. Further, we validate the analytical model of CFE through simulations in NS-3 and compare the performance of GARP with three benchmark algorithms.

• Journal of IKEEE
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• v.21 no.4
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• pp.416-419
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• 2017

In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.