• Proceedings of the KIEE Conference
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• 2002.06a
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• pp.55-59
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• 2002

This paper presents a novel three-phase current-fed Pulse Width Modulation converter with switched capacitor type resonant DC link commutation circuit operating PWM pattern strategy under a design consideration of low-pass filter, which can operate on the basis of the principle of zero current soft switching commutation. In the first place, the steady state operating principle of this converter with a new resonant DC link snubber circuit is described in connection with the equivalent operation circuit, together with the practical design procedure of the switched-capacitor type resonant DC link circuit is discussed from a theoretical viewpoint on the basis of a design example for high-power applications. The actively delayed time correction method to compensate distorted currents due to a relatively long resonant commutation time is newly implemented in the open loop control scheme so as to acquire the new optimum PWM pattern. Finally, the experiment of set-up in laboratory system of this converter is concretely demonstrated herein to confirm a zero current soft-switching commutation of this converter. The comparative evaluations between current -fed hard switching PWM and soft-switching PWM converters are carried out from a viewpoint of their PWM converter characteristics.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.2
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• pp.49-55
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• 2003

This paper presents a novel three-phase current-fed Pulse Width Modulation converter with switched capacitor type resonant DC link commutation circuit operating PWM pattern strategy under a design consideration of low-pass filter, which can operate on the basis of the principle of zero current soft switching commutation. In the first place, the steady state operating principle of this converter with a new resonant DC link snubber circuit is described in connection with the equivalent operation circuit, together with the practical design procedure of the switched-capacitor type resonant DC link circuit is discussed from a theoretical viewpoint on the basis of a design example for high-power applications. The actively delayed time correction method to compensate distorted currents due to a relatively long resonant commutation time is newly implemented in the open loop control scheme so as to acquire the new optimum PWM pattern. Finally, the experiment of set-up in laboratory system of this converter is concretely demonstrated herein to confirm a zero current soft-switching commutation of this converter. The comparative evaluations between current-fed hard switching PWM and soft-switching PWM converters are carried out from a viewpoint of their PWM converter characteristics.

• ETRI Journal
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• v.31 no.2
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• pp.234-236
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• 2009

We present a novel operational amplifier preset technique for a switched-capacitor circuit to reduce the acquisition time by improving the slewing. The acquisition time of a variable gain amplifier (VGA) using the proposed technique is reduced by 30% compared with a conventional one; therefore, the power consumption of the VGA is decreased. For additional power reduction, a programmable capacitor array scheme is used in the VGA. In the 0.13 ${\mu}m$ CMOS process, the VGA, which consists of three-stages, occupies 0.33 $mm^2$ and dissipates 19.2 mW at 60 MHz with a supply voltage of 1.2 V. The gain range is 36.03 dB, which is controlled by a 10-bit control word with a gain error of ${\pm}0.68$ LSB.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1402-1412
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• 2017

This paper presents a new high step-up dc/dc converter for renewable energy systems in which a high voltage gain is provided by using a coupled inductor. The operation of the proposed converter is based on a charging capacitor with a single power switch in its structure. A passive clamp circuit composed of capacitors and diodes is employed in the proposed converter for lowering the voltage stress on the power switch as well as increasing the voltage gain of the converter. Since the voltage stress is low in the provided topology, a switch with a small ON-state resistance can be used. As a result, the losses are decreased and the efficiency is increased. The operating principle and steady-states analyses are discussed in detail. To confirm the viability and accurate performance of the proposed high step-up dc-dc converter, several simulation and experimental results obtained through PSCAD/EMTDC software and a built prototype are provided.

• Proceedings of the KIPE Conference
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• 2014.11a
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• pp.163-164
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• 2014

전력계통은 전력수요의 지속적인 성장에 따라서 전력설비의 추가를 지속적으로 추진하고 있지만, 심해지는 환경문제 등으로 인해 용지 확보에 어려움이 있다. 이로 인해 송전선로 장거리화, 용량부족량 등 전력계통에 여러 가지 복잡한 문제가 야기되는데. 이것은 곧 전력계통의 안정도와 직결된다. 이러한 문제를 효과적이면서 경제적인 해결방법으로 FACT(Flexible AC Transmission System)기술이 주목 받고 있다. FACTS 기기 중 SVC(Static Var Compensator)는 상용운전 중이며, 기존 동기조상기에 비해 저렴하고, 신속 정확한 전압제어를 하는 장점이 있다. SVC는 TCR(Thyristor Controlled Reactor)과 TSC(Thyristor Switched Capacitor), FC(Fixed Capacitor)등 여러 종류의 구성을 가지고 있다. 합성시험회로설비(Synthetic Test Circuit)는 Thyristor로 구성된 TCR, TSC Valve를 실제 운전조건으로 동작시켜 SVC Valve의 신뢰성을 검증하는 설비이다. 특히, TSC Valve는 운전시 초기 과전류가 발생하는 운전특성상 이에 대한 평가기준에 따른 시험을 통해 신뢰성을 반드시 검증하여야 한다. 본 논문에서는 IEC 61954에서 제시하는 시험평가 기준에 의거하여 TSC의 Overcurrent Test를 위한 STC 평가 방법를 기술하고 설계된 TSC 시험을 위한 STC topology와 Simulation으로 검증 방법을 기술한다.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1187-1194
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• 2017

In this paper, a high step-up DC-DC PWM converter with continuous input current and low voltage stress is presented for renewable energy application. The proposed converter is composed of a boost converter integrated with an auxiliary step-up circuit. The auxiliary circuit uses an additional coupled inductor and a balancing capacitor with voltage doubler and switching capacitor technique to achieve high step-up voltage gain with an appropriate switch duty cycle. The switched capacitors are charged in parallel and discharged in series by the coupled inductor, stacking on the output capacitor. In the proposed converter, the voltage stress on the main switch is clamped, so a low voltage switch with low ON resistance can be used to reduce the conduction loss which results in the efficiency improvement. A detailed discussion on the operating principle and steady-state analyses are presented in the paper. To justify the theoretical analysis, experimental results of a 200W 40/400V prototype is presented. In addition, the conducted electromagnetic emissions are measured which shows a good EMC performance.

• Journal of Power Electronics
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• v.17 no.3
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• pp.579-589
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• 2017

In this study a new high step-up dc-dc converter is presented. The operation of the proposed converter is based on the capacitor switching and coupled inductor with a single active power switch in its structure. A passive voltage clamp circuit with two capacitors and two diodes is used in the proposed converter for elevating the converter's voltage gain with the recovered energy of the leakage inductor, and for lowering the voltage stress on the power switch. A switch with a low $R_{DS}$ (on) can be adopted to reduce conduction losses. In the generalized mode of the proposed converter, to reach a desired voltage gain, capacitor stages with parallel charge and series discharge techniques are extended from both sides of secondary side of the coupled inductor. The proposed converter has the ability to alleviate the reverse recovery problem of diodes with circuit parameters. The operating principle and steady-states analyses are discussed in detail. A 40W prototype of the proposed converter is implemented in the laboratory to verify its operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.989-998
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• 2012

A ratio type of capacitance measurement circuit is proposed to measure an extremely small value of the fF capacitance on this paper. This measurement circuit is formed with a switched-capacitor integrator, a comparator, and logic circuit blocks to control the switches. It converts the measured ratio value between the known value of on-chip capacitor and the unknown value of capacitor to the digital signal. The fF capacitance with minimized error can be obtained by calculating this ratio. This proposed circuit is designed with standard CMOS $0.18{\mu}m$ process, and various HSpice simulations prove that this capacitance measurement circuit is able to measure the capacitance under 5fF with less than ${\pm}0.3%$ error rate.

• Journal of Advanced Marine Engineering and Technology
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• v.31 no.8
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• pp.975-982
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• 2007

The single-phase switched reluctance motor(SRM) drive requires DC source which is generally supplied through a rectifier connected with a commercial source. The rectifier is consist of a diode full bridge and a filter circuit. Usually the filter circuit uses capacitor with large value capacitance to reduce ripple component of DC power. Although the peak torque ripple of SRM is small, the short charge and discharge current of the filter capacitor draws the low power factor and system efficiency. A modified single phase SRM drive system is presented in this paper, which includes drive circuit realizing reduction of torque ripple and improvement of power factor. In the proposed drive circuit, one switching part and diode which can separate the output of AC/DC rectifier from the filter capacitor is added. Also, a upper switch of drive circuit is exchanged a diode in order to reduce power switching device. Therefore the number of power switch device is not changed, two diodes are only added in the SRM drive. To verify the proposed system, some simulation and experimental results are presented.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.3
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• pp.13-18
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• 2010

This work proposes and characterizes switched-capacitor type cyclic digital-to-analog converter for display data driving. The proposed digital-to-analog converter composes simple structure, and can be implemented for low-power, small area display driver ICs. By circuit level simulations, it is verified that the op-amp input referred offset is attenuated at the DAC output and the circuit performance is robust at 0.5% of capacitor mismatch.