• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.10
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• pp.1-12
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• 1993

A multiprocessor system for high-speed processing of hybrid image coding algorithms such as H.261, MPEG, or Digital HDTV is presented in this study. Using a combination of highly parallel 32-bit microprocessor, DCT(Discrete Cosine Transform), and motion detection processor, a new processing module is designed for the implementation of high performance coding system. The sysyem is implemented to allow parallel processing since a single module alone cannot perform hybrid coding algorithms at high speed, and crossbar switch is used to realize various parallel processing architectures by altering interconnections between processing modules within the system.

• Journal of Magnetics
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• v.16 no.3
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• pp.263-267
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• 2011

The present paper proposes a novel cableless magnetic actuator with a new propulsion module that exhibits a very high thrusting force. This actuator contains an electrical inverter that directly transforms DC from button batteries into AC. The electrical DC-AC inverter incorporates a mass-spring system, a reed switch, and a curved permanent magnet that switches under an electromagnetic force. The actuator is moved by the inertial force of the mass-spring system due to mechanical resonance energy. The experimental results show that the actuator is able to move upward at a speed of 33 mm/s when using 10 button batteries when pulling a 10 g load mass. This cableless magnetic actuator has several possible applications, including narrow-pipe inspection and maintenance.

• BMB Reports
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• v.52 no.4
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• pp.227-238
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• 2019

GROWTH-REGULATING FACTORs (GRFs) are sequence-specific DNA-binding transcription factors that regulate various aspects of plant growth and development. GRF proteins interact with a transcription cofactor, GRF-INTERACTING FACTOR (GIF), to form a functional transcriptional complex. For its activities, the GRF-GIF duo requires the SWITCH2/SUCROSE NONFERMENTING2 chromatin remodeling complex. One of the most conspicuous roles of the duo is conferring the meristematic potential on the proliferative and formative cells during organogenesis. GRF expression is post-transcriptionally down-regulated by microRNA396 (miR396), thus constructing the GRF-GIF-miR396 module and fine-tuning the duo's action. Since the last comprehensive review articles were published over three years ago, many studies have added further insight into its action and elucidated new biological roles. The current review highlights recent advances in our understanding of how the GRF-GIF-miR396 module regulates plant growth and development. In addition, I revise the previous view on the evolutionary origin of the GRF gene family.

• Smart Media Journal
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• v.8 no.3
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• pp.47-52
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• 2019

In this paper, we designed HW / SW interfaces for processing the signals of capacitive sensors like Electric Potential Sensor (EPS) to detect the surrounding electric field disturbance as feature signals in motion recognition systems. We implemented a smart light control system with those interfaces. In the system, the on/off switch and brightness adjustment are controlled by hand gestures using the designed and fabricated interface circuits. PWM (Pulse Width Modulation) signals of the controller with a driver IC are used to drive the LED and to control the brightness and on/off operation. Using the hand-gesture signals obtained through EPS sensors and the interface HW/SW, we can not only construct a gesture instructing system but also accomplish the faster recognition speed by developing dedicated interface hardware including control circuitry. Finally, using the proposed hand-gesture recognition and signal processing methods, the light control module was also designed and implemented. The experimental result shows that the smart light control system can control the LED module properly by accurate motion detection and gesture classification.

• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.6
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• pp.269-279
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• 2020

This paper presents the design and implementation of embedded systems and autonomous path generation for autonomous speed sprayer. Autonomous Orchard Systems can be divided into embedded controller and path generation module. Embedded controller receives analog sensor data, on/off switch data and control linear actuator, break, clutch and steering module. In path generation part, we get 3D cloud point using Velodyne VLP16 LIDAR sensor and process the point cloud to generate maps, do localization, generate driving path. Then, it finally generates velocity and rotation angle in real time, and sends the data to embedded controller. Embedded controller controls steering wheel based on the received data. The developed autonomous speed sprayer is verified in test-bed with apple tree-shaped artworks.

• Proceedings of the Korean Society for Emotion and Sensibility Conference
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• 2004.11a
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• pp.36-36
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• 2004

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.417-417
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• 2004

• Journal of Power Electronics
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• v.7 no.4
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• pp.343-352
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• 2007

This paper proposes a modularized charge equalization converter for hybrid electric vehicle (HEV) lithium-ion battery cells, in which the intra-module and the inter-module equalizer are Implemented. Considering the high voltage HEV battery pack, over approximately 300V, the proposed equalization circuit modularizes the entire $M^*N$ cells; in other words, M modules in the string and N cells in each module. With this modularization, low voltage stress on all the electronic devices, below roughly 64V, can be obtained. In the intra-module equalization, a current-fed DC/DC converter with cell selection switches is employed. By conducting these selection switches, concentrated charging of the specific under charged cells can be performed. On the other hand, the inter-module equalizer makes use of a voltage-fed DC/DC converter for bi-directional equalization. In the proposed circuit, these two converters can share the MOSFET switch so that low cost and small size can be achieved. In addition, the absence of any additional reset circuitry in the inter-module equalizer allows for further size reduction, concurrently conducting the multiple cell selection switches allows for shorter equalization time, and employing the optimal power rating design rule allows fur high power density to be obtained. Experimental results of an implemented prototype show that the proposed equalization scheme has the promised cell balancing performance for the 7Ah HEV lithium-ion battery string while maintaining low voltage stress, low cost, small size, and short equalization time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1164-1170
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• 2002

In the ACE2000 MPLS system, MPLS Interface Module(MIM) is composed of an ATM Interface Module and a HFMA performing a packet forwarding. In the MIM, the HFMA RSAR receive cells from the Physical layer and reassemble the cells. And the IP Lookup controller perform a packet forwarding after packet classification. Forwarded packet is segmented into cells in the HFMA TSAR and transfer to the ALMA for the transmission to an ATM cell switch. When the MIM make use of an ATM Interface Module, it directly connect the ALMA with a PHY layer using the UTOPIA Level2 interface. Then, an ALMA performs Master Mode. Also, the HFMA TSAR performs the Master Mode in the MIM. Therefore, the UTOPIA-L2 Controller of the Slave Mode require for interfacing between an ALMA and a HFHA TSAR. In this paper, we implement the architecture and cell control mechanism for the UTOPIA-L2 Controller supporting Multi-ports.

• Journal of Internet Computing and Services
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• v.3 no.5
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• pp.9-17
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• 2002

CSIX-L1 is the Common Switch Interface that defines a physical interface for transferring information between a traffic manager (Network Processor) and a switching fabric in ATM, IP, MPLS, Ethernet and data communication areas. In Tx, data to be transmitted is generated in Cframe which is the base information unit and in Rx, original data is extracted from the received Cframe. CSIX-L1 suppots the 32, 64, 96, and 123-bit interface and generates a variable length CFrame and Idle Cframe. Also CSIX-L1 appends Padding byte and supports 16-bit Vertical parity, CSIX-L1 is designed using Xilinx 4,1i. After functional and timing simulations are completed. CSIX-L1 module is downloaded in Xilinx FPGA XCV1000EHQ240C and verified. The synthesized CSIX module operates at 27MHz.