• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.6
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• pp.34-43
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• 2008

The state-space average model is extended to buck-boost, and buck-boost topology switching mode DC/DC converters and modified to have higher precision without increment of computation. The modified model is used in continuous conduction mode(CCM) switching DC/DC converters and some significant conclusions are derived. This paper discusses the discontinuous conduction mode(DCM) modeling of DC/DC converter and critical characteristic using average model of switch. Average model of switch approach is expended to the modeling of boundary conduction mode DC/DC converters that operate at the boundary between continuous conduction mode(CCM) and discontinuous conduction mode(DCM). Frequency responses predicted by the average model of switch are verified by simulation and experiment. A prototype featuring 15[V] input voltage, 24[V] output voltage, and 24[W] output power using MOSFET.

• Journal of KIISE:Information Networking
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• v.32 no.2
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• pp.244-253
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• 2005

In this paper, a performance evaluation model of the switch router with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the crossbar switch. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. The performance of the multiple-buffered crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a network that uses the multiple buffered crossbar switches. Less than $2\%$ differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• Journal of the Korea Society of Computer and Information
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• v.8 no.3
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• pp.100-106
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• 2003

This paper presents the design of a value-added ATM switch. The ATM switch ca perform CAC Processing and Firewall Processing Routine at packet-level (IP) at the ATM environment per port. The proposed two routine are integrated into the components of ATM switch. The Firewall switch employs a suggested two routine model to avoid or reduce the latency caused by filtering. Also, we suggest four classes are defined. namely, classes A, B, C, and D, which are orded from the safest to the most dangerous. The suggested model performance of ATM Firewall switch is estimated simulation in terms of the throught and latency by computer.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2007.04a
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• pp.485-488
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• 2007

최근 Analog Sampled-Data 신호처리를 위하여 주목되고 있는 SI(Switched-Current) circuit은 저전력 동작을 하는 장점이 있지만, 반면에 SI circuit에서의 기본 회로인 Current Memory는 Charge Injection에 의한 Clock Feedthrough이라는 치명적인 단점을 갖고 있다. 따라서 본 논문에서는 Current Memory의 문제점인 Clock Feedthrough의 일반적인 해결방안으로 Dummy Switch의 연결을 검토하였고, Austria Mikro Systeme(AMS)에서 $0.35{\mu}m$ CMOS process BSIM3 Model로 제작하기 위하여 Current Memory의 Switch MOS와 Dummy Switch MOS의 적절한 Width을 정의하여야 하므로, 그 값을 도출하였다. Simulation 결과, Switch의 Width는 $2{\mu}m$, Dummy Switch의 Width는 $2.35{\mu}m$로 정의될 수 있음을 확인하였다.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2484-2496
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• 2000

High speed switches have been developing to interconnect a large number of nodes. It is important to analyze the switch performance under various conditions to satisfy the requirements. Queueing analysis, in general, has the intrinsic problem of large state space dimension and complex computation. In fact, The petri net is a graphical and mathematical model. It is suitable for various applications, in particular, manufacturing systems. It can deal with parallelism, concurrence, deadlock avoidance, and asynchronism. Currently it has been applied to the performance of computer networks and protocol verifications. This paper presents a framework for modeling and analyzing ATM switch using stochastic activity networks (SANs). In this paper, we provide the ATM switch model using SANs to extend easily and an approximate analysis method to apply A TM switch models, which significantly reduce the complexity of the model solution. Cell arrival process in output-buffered Queueing A TM switch with finite buffer is modeled as Markov Modulated Poisson Process (MMPP), which is able to accurately represent real traffic and capture the characteristics of bursty traffic. We analyze the performance of the switch in terms of cell-loss ratio (CLR), mean Queue length and mean delay time. We show that the SAN model is very useful in A TM switch model in that the gates have the capability of implementing of scheduling algorithm.

• Journal of information and communication convergence engineering
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• v.9 no.1
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• pp.74-77
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• 2011

PSPICE modeling of a commercial LED driver IC (TOP245P) and PC817A optocoupler is proposed for the switch-mode power supply (SMPS) (applicable to LED driver) design and simulation. An analog behavioral model of the TOP245P IC including the shunt regulator, under-voltage(UV) detection, over-voltage(OV) shut-down and SR flip-flop is developed by using PSPICE. The empirical equation of PC817A current transfer ratio (CTR) is fitted from the datasheet of PC817A. Two types of SMPSs are simulated with the averaged-model and switching-model. The simulation results by the proposed PSPICE models are in good agreement with those in the data sheet and an experimental data.

• Journal of Electrical Engineering and Technology
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• v.11 no.3
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• pp.575-584
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• 2016

Considering the randomness and uncertainty of wind power, a reliability model of WTGs is established based on the combination of the Weibull distribution and the Markov chain. To analyze the failure mode quickly, we use the switch-section partitioning method. After defining the first-level load zone node, we can obtain the supply power sets of the first-level load zone nodes with each WTG. Based on the supply sets, we propose the dynamic division strategy of island operation. By adopting the fault analysis method with the attributes defined in the switch-section, we evaluate the reliability of the distribution network with WTGs using a sequential Monte Carlo simulation method. Finally, using the IEEE RBTS Bus6 test system, we demonstrate the efficacy of the proposed model and method by comparing different schemes to access the WTGs.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.21 no.9
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• pp.42-49
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• 2022

An underground electric switch is a high-voltage switch used in distribution network systems for a reliable power supply. Many studies are being conducted to expand the switch to use an eco-friendly gas using dry air instead of SF6 gas to reduce greenhouse gas emissions. In this study, a flow analysis model was established to improve the performance of an eco-friendly gas switch. The results were compared and reviewed through experiments. For the optimal arc grid design applied to the switch, the flow characteristics based on the flow path configuration and the changes in arcing time for each configuration were compared. Flow analysis can predict the switch flow distribution, and a comparative review of the flow path configurations of various methods is possible.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1756-1764
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• 1996

In this paper, we propose a new switch element of buffered Banyan network and analysis it. The proposed switch element consists of CASO(Content ASsociated Output) buffers, its controller and 2*2 crossbar switch. This switch element increase the performance of buffered Banyan network by removing HOL blocking. Also, we analyze the proposed switch element by mathematical modelling method based on MY analysis model which is one of earier proposed models.

• Journal of Korea Multimedia Society
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• v.13 no.12
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• pp.1805-1813
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• 2010

In this paper, we address the issue of how to improve performance of integrated optical path and optical packet. For supporting ultra-high-speed traffic, integration of optical paths and packets in a switch is one of key techniques in New Generation Networks. However, the wavelength allocation for optical packets and optical paths has not been efficiently resolved yet because there lacks of a systematic model for evaluating performance of the integrated switch. This paper models the operation of the integrated switch as a system of two servers, one for optical paths and the other for optical packets. From the model, we utilize Newton method to find an optimal policy for sharing of wavelength resources. Afterwards, we propose an algorithm to dynamically allocate wavelength resources in an integrated switch. Finally, we evaluate performance of that algorithm.