• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.141-145
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• 2021

The brightness of the Organic Light Emitting Diode (OLED) display is controlled by thin-film transistors (TFTs). Regardless of the materials and the structures of TFTs, an OLED suffers from the instable threshold voltage (V_th) of a TFT during operation. When designing an OLED pixel with circuit simulation tool such as SPICE, a designer needs to take V_th shift into account to improve the reliability of the circuit and various compensation methods have been proposed. In this paper, the effect of the compensation circuits from two typical OLED pixel circuits proposed in the literature are studied by the transient simulation with a SPICE tool in which the stretched-exponential time dependent V_th shift function is implemented. The simulation results show that the compensation circuits improve the reliability at the beginning of each frame, but V_th shifts from all TFTs in a pixel need to be considered to improve long-time reliability.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.249-254
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• 2011

This paper describes an efficient design of the interpolation circuit to generate the luma and chroma sub-pixels for H.264 motion estimation. The circuit based on the proposed architecture does not require any input data buffering and processes the horizontal, vertical and diagonal sub-pixel interpolations in parallel. The performance of the circuit is further improved by simultaneously processing the 1/2-pixel and 1/4-pixel interpolations for luma components and the 1/8-pixel interpolations for chroma components. In order to reduce the circuit size, we store the intermediate data required to process all the interpolations in parallel in the internal SRAM's instead of registers. We described the proposed circuit at register transfer level and verified its operation on FPGA board. We also synthesized the gate-level circuit using 130nm CMOS standard cell library. It consists of 20,674 gates and has the maximum operating frequency of 244MHz. The total number of SPSRAM bits used in our circuit is 3,232. The size of our circuit (including logic gates and SRAM's) is smaller than others and the performance is still comparable to them.

• Journal of the Semiconductor & Display Technology
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• v.9 no.2
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• pp.79-85
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• 2010

In this paper, we propose a web inspection system (WIS) for real-time detection of paper defects which can cause critical fractures during papermaking process. Our system incorporates high speed line-scan camera, lighting system, and detection algorithm to provide robust and precise detection of paper defects in real-time. Since edge defects are very crucial to the paper fractures, our system focuses on the edge region of the paper instead of inspecting the whole paper area. In our algorithm, image projection and sub-pixel operation are utilized to detect the edge defects precisely and connected component labeling and shape analysis techniques are adopted to extract various kinds of the region defects. Experimental results revealed that our web inspection system is very efficient for detecting paper defects during papermaking processes.

• Journal of IKEEE
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• v.19 no.1
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• pp.1-9
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• 2015

This paper proposes the design of sub-pixel interpolation circuit for real-time multi-decoder supporting 4K-UHD video images. The proposed sub-pixel interpolation circuit supports H.264, MPEG-4, VC-1 and new video compression standard HEVC. The common part of the interpolation algorithm used in each video compression standard is shared to reduce the circuit size. An intermediate buffer is effectively used to reduce the circuit size and optimize the performance. The proposed sub-pixel interpolation circuit was synthesised by using 130nm standard cell library. The synthesized gate-level circuit consists of 122,564 gates and processes 35~86 image frames per second for 4K-UHD video at the maximum operation frequency of 200MHz. Therefore, the proposed circuit can process 4K-UHD video in real time.

• Journal of the Korea Computer Industry Society
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• v.2 no.9
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• pp.1183-1190
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.169-172
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2521-2524
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• 2002

In this paper, We propose an Image processing algorithm for a paper-cup inner defect inspection. First, we devide a cup image to four sections considering the characteristic of a cup and filter noises limit by using the flood-fill algorithm and median filter. Second, to obtain the clearer inspection result of the edge point inner cup, We apply the sharpening convolution filer to the objected inspect the edge points by using the LOG edge detector. Third, executing sub-pixel operation with the orignal image, we find the defect parts in the cup. Finally, denoting the inspected defect parts as rectangular, we recompose the images of the defected ones.

• Journal of the Optical Society of Korea
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• v.17 no.5
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• pp.392-398
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• 2013

As the essential techniques for the CD (Critical Dimension) measurement of the LCD pattern, there are various modules such as an optics design, auto-focus [1-4], and precise edge detection. Since the operation of image enhancement to improve the CD measurement repeatability, a ring type of the reflected lighting optics is devised. It has a simpler structure than the transmission light optics, but it delivers the same output. The edge detection is the most essential function of the CD measurements. The CD measurement is a vital inspection for LCDs [5-6] and semiconductors [7-8] to improve the production yield rate, there are numbers of techniques to measure the CD. So in this study, a new subpixel algorithm is developed through facet modeling, which complements the previous sub-pixel edge detection algorithm. Currently this CD measurement system is being used in LCD manufacturing systems for repeatability of less than 30 nm.

• Journal of the Semiconductor & Display Technology
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• v.8 no.2
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• pp.23-29
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• 2009

To increase the data capacity of one-dimensional symbology, 2D barcodes have been proposed a decade ago. In this paper, a new 2D barcode detection algorithm based on Local Binary Pattern is presented. To locate 2D barcode symbols, a texture analysis scheme based on the Local Binary Pattern is adopted, and a gray-scale projection with sub-pixel operation is utilized to separate the symbol precisely from the input image. Finally, the segmented symbol is normalized using the inverse perspective transformation for the decoding process. The proposed method ensures high performances under various lighting/printing conditions and strong perspective deformations. Experiments show that our method is very robust and efficient in detecting the symbol area for the various types of 2D barcodes.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.37 no.2
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• pp.55-62
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• 2019

The stereo geometry establishment based on the precise sensor modeling is prerequisite for accurate stereo data processing. Ground control points are generally required for the accurate sensor modeling though it is not possible over the area where the accessibility is limited or reference data is not available. For the areas, the relative orientation should be carried out to improve the geometric consistency between the stereo data though it does not improve the absolute positional accuracy. The relative orientation requires conjugate points that are well distributed over the entire image region. Therefore the automatic conjugate point extraction is required because the manual operation is labor-intensive. In this study, we applied the method consisting of the key point extraction, the search space minimization based on the epipolar line, and the rigorous outlier detection based on the RPCs (Rational Polynomial Coefficients) bias compensation modeling. We tested different parameters of window sizes for Kompsat-2 across track stereo data and analyzed the RPCs precision after the bias compensation for the cases whether the epipolar line information is used or not. The experimental results showed that matching outliers were inevitable for the different matching parameterization but they were successfully detected and removed with the rigorous method for sub-pixel level of stereo RPCs precision.