• 한국진공학회지
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• 제8권4A호
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• pp.410-416
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• 1999

It is confirmed that the cause of anode current in SEDs (surface conduction electron emission displays) is the inertial force of electron emitted from the cathode surface in the calculation of electron trajectory. In the fissure of sub-micron, most of electrons emitted from the area of the cathode edge flow into the coplanar anode, while some electrons are emitted into the display surface by the current ratio of $10^{-3}$. The later electrons are forced to fly into the display surface by the centrifugal force due to the curved electric field between top side surfaces near the fissure.

• Current Optics and Photonics
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• 제4권1호
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• pp.16-22
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• 2020

In high resolution imaging devices, smaller aperture in the color filter causes cross talk which provides incorrect information. Plasmonic color filters (PCFs) have been reported as an alternative of the conventional color resist based-color filter (CRCF) and many studies on PCFs demonstrated the filtering function by PCFs with a sub-micron size. In this work, we investigated the cross talk performance of PCFs compared to CRCFs. The effect of cross talk over distance from the filter were measured for each filter. Despite poorer spectral filtering characteristics, PCFs were more robust against cross talk than CRCFs. Also, the further away from the filter, the more cross talk appeared. As a result, PCFs showed less cross talk than CRCFs at about 82% of the results measured at a distance of 2~10 ㎛. This study will help to make practical use of PCFs in high-resolution imaging applications.

• 전자공학회논문지A
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• 제33A권12호
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• pp.65-71
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• 1996

A novel lateral field emitter triode has been designed and fabricated. It has self-vacuum environmets and low turn-on voltage, so that the chief problems of previous field emission devices such as additional vacuum sealing process and high turn-on voltage are settled. An in-situ vaccum encapsulation empolying recessed cavities by isotropic RIE (reactive ion etch) method and an electron beam evaporated molybdenum vacuum seals are implemented to fabricate the new field emitter triode. The device exhibits low turn-on voltage of 7V, stabel current density of 2.mu.A/tip at V$_{AC}$ = 30V, and high transconductance (g$_{m}$) of 1.7$\mu$S at V$_{AC}$ = 22V. The superb device characteristics are probably due to sub-micron dimension device structure and the pencil type lateral cathode tip employing upper and lower LOCOS oxidation.

• 산업기술연구
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• 제22권B호
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• pp.241-249
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• 2002

Optical fiber is indispensable for optical communication systems that transmit large volumes of data at high speed, but super precision technology in sub-micron units is required for optical axis adjustment. We developed the automatic optical fiber by image processing and automatic loading system. we have developed 6-axis micro stage system for I/O optical fiber arrays, the initial automatic aligning system software for a input optical array by the image processing technique, fast I/O-synchronous aligning strategy, the automatic loading/unloading system and the automatic UV bonding mechanism. In order to adjust the alignment it used on PC based motion controller, a $10{\mu}m$ repeat-detailed drawing of automatic loading system is developed by a primary line up for high detailed drawing. Also, at this researches used the image processing system and algorithm instead of the existing a primary hand-line up and fiber input array and waveguide chip formed in line by automatic.

• 한국결정성장학회지
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• 제14권2호
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• pp.47-49
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• 2004

Gate protection $SiN_x$ as an alternative to a conventional re-oxidation process in Dynamic Random Access Memory devices is investigated. This process can not only protect the gate electrode tungsten against oxidation, but also save the thermal budget due to the re-oxidation. The protection $SiN_x$ process is applied to the poly-Si gate, and its device performance is measured and compared with the re-oxidation processed poly-Si gate. The results on the gate dielectric integrity show that etch damage-curing capability of protection $SiN_x$ is comparable to the re-oxidation process. In addition, the hot carrier immunity of the $SiN_x$ deposited gate is superior to that of re-oxidation processed gate.

• 한국수소및신에너지학회논문집
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• 제18권3호
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• pp.238-243
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• 2007

The composite powder of Cu and YSZ was synthesized for a high temperature electrolysis cathode by mechanical milling. The average Cu particle size was reduced to 5 micro-meter from 48 micro-meter after the mechanical ball milling. The composite powder showed that Cu particles were uniformly covered with finer YSZ particles. Sub-micron sized pores were uniformly dispersed in the Cu/YSZ composit. Homogeneously-dispersed fine YSZ in the composite is expected to the increase in triple phase boundaries, thereby leading the enhanced performance of cathode.

• E2M - 전기 전자와 첨단 소재
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• 제7권2호
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• pp.157-164
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• 1994

DRAM(Dynamic Random Access Memory)은 반도체 소자중 가장 대표적인 기억소자로, switch역활을 하는 1개의 transistor와 data의 전하를 축적하는 1개의 capacitor로 구성된 단순한 구조와 고집적화에 용이하다는 이점을 바탕으로, supercomputer에서 가전제품 및 산업기기에 이르기 까지 널리 이용되어왔다. 한편으로 DRAM사업은 고가의 장치사업으로 조기시장 진입을 위하여 초기에 막대한 자본투자, 급속한 기술발전, 짧은 life cycle, 가격급락등이 심하여, 시한내 투자회수가 이루어져야 하는 위험도가 큰 기회사업이라는 양면성도 가지고 있다. 이러한 관점때문에 새로운 DRAM기술은 매 세대마다 끊임없이 빠른 속도로 개발되어왔다. 그러나 sub-micron이하의 DRAM세대로 갈수록 그에 대한 신기술은 점차 어렵게 되어가고, 한편으로는 system의 다양화에 따른 요구도 강하여, 이제는 통상적인 DRAM의 고집적화/저가의 전략만으로는 생존하기 어려운 실정이므로 개발전략도 수정하여야만 할 것이다. 이러한 어려운 기술한계를 극복하기 위하여 새로운 소자기술 및 공정개발에 대한 breakthrough가 이루어져야 할 것이다. 이러한 관점에서 현재까지의 DRAM개발 추이와 향후의 기술방향에 관하여 몇가지 중요한 item을 설정하여 논의해 보기로 한다.

• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.838-843
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• 2002

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.445-446
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• 2008

With the semiconductor industry evolving into the deep sub-micron (DSM) era, the crosstalk effects on interconnect lines of a chip have increasingly caused a major bottleneck for design closure. In this paper, we propose an effective design guide line to reduce cell area overhead without crosstalk noise violations by using crosstalk prevention flow with clock shielding.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.687-690
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• 2003

Experimental results are presented for gate oxide degradation and its effect on device parameters under negative and positive bias stress conditions using NMOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both hole- and electron-trapping are found to dominate the reliability of gate oxide. However, with changing gate voltage polarity, the degradation becomes dominated by electron trapping. Statistical parameter variations as well as the "OFF" leakage current depend on those charge trapping. Our results therefore show that Si or O bond breakage by electron can be another origin of the investigated gate oxide degradation.gradation.