• Bulletin of the Korean Chemical Society
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• v.35 no.6
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• pp.1879-1882
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• 2014

• Journal of KIISE:Software and Applications
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• v.32 no.10
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• pp.949-955
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• 2005

In this Paper, we propose fast block matching algorithm by dividing complex areas based on complexity order of reference block and square sub-block to reduce an amount of computation of full starch(FS) algorithm for fast motion estimation, while keeping the same prediction quality compared with the full search algorithm. By using the fact that matching error is proportional to the gradient of reference block, we reduced unnecessary computations with square sub-block adaptive matching scan based image complexity instead of conventional sequential matching scan and row/column based matching scan. Our algorithm reduces about $30\%$ of computations for block matching error compared with the conventional partial distortion elimination(PDE) algorithm without any prediction quality, and our algorithm will be useful in real-time video coding applications using MPEG-4 AVC or MPEG-2.

• Journal of Broadcast Engineering
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• v.9 no.1
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• pp.54-63
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• 2004

A new motion compensated frame Interpolation (MCI) algorithm by block based motion estimation (BME) is proposed. The block for the BME is composed of a large overlapped block for practical object motion estimation (ME) and a small block (which has a coinciding center with the ME-block) for the more precise motion compensated image description. Pixels in the block for the ME are sub-sampled to reduce computational complexity. The proposed method is executed with the various ME-blocks which have different size and sub-sampling ratio, and compared to the conventional method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1451-1459
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• 2004

In this paper, a low-power 32-point IMDCT structure is proposed for MP3. Through re-odering of IMDCT matrices, we propose the systolic structure operating with 16, 8, 4, 2, and 1 cycle, respectively. To reduce power consumption, multiplication of each sub blocks are implemented by add and shift operation with CSD(Canrmic sigled digit) form coefficients. To reduce, furthermore, the number of adders, we utilize the common sub-expression sharing techniques. With these techniques, the relative power consumption of the proposed structure is reduced by 58.4% comparison to the conventional structure using only 2's complement form coefficient. Validity of the proposed structure is proved through Verilog-HDL coding.

• ETRI Journal
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• v.31 no.1
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• pp.80-82
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• 2009

In this letter, a new intra-block coding mode is presented to improve the coding efficiency for band-limited signals. A band-limited block is sub-sampled, and the sub-sampled signal is coded on the basis of the conventional prediction/transform coding. The rest of the samples are reconstructed by interpolation at the decoder side without any side information. Experimental results show that the proposed algorithm achieves coding gains of 2.7% for common intermediate format (CIF), 4.29% for quarter CIF, and 6.39% for 720p60 sequences against the H.264/AVC JM10.2 reference software.

• Journal of Korea Multimedia Society
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• v.12 no.4
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• pp.483-491
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• 2009

In this paper, we propose a fast motion estimation algorithm using adaptive elimination of sub-block partial coefficients. The proposed algorithm predicts an adaptive threshold for each sub-block by using relationship of an initial sum of absolute difference(SAD) and a minimum SAD at the current point, and efficiently reduces unnecessary calculation time of the conventional partial distortion elimination(PDE) algorithm with the predicted threshold. Our algorithm reduces about 60% of computations of the conventional PDE algorithm without any degradation of prediction quality compared with the con ventional full search. Additionally, the proposed algorithm can be applied to other fast motion estimation 떠gorithms. the proposed Our proposing algorithm will be useful to real-time video coding applications using MPEG-2 or MPEG-4 AVC standards.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1121-1125
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• 2004

This paper is studied the fast block mode decision algorithm for H.264/AVC. The fast block mode decision algorithm is consist of block range decision and merge algorithm. The block range decision algorithm classifies the block over 8$\times$8 size or below for 16$\times$16 macroblock to decide the size and type of sub blocks. The block over 8$\times$8 size is divided into the blocks of 16$\times$8, 8$\times$16 and 16$\times$16 size using merging algorithm which is considered MVD(motion vector difference) of 8$\times$8 block. The sub block range decision reduces encoding arithmetic amount by 48.25% on the average more than the case not using block range decision.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.178-180
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• 2004

In this work, we propose new method of sigma filtering for efficient filtering and preserving edge regions in DCT Domain. In block-based image compression technique, the image is first divided into non-overlapping $8{\times}8$ blocks. Then, the two-dimensional DCT is computed for each $8{\times}8$ block. Once the DCT coefficients are obtained, they are quantized using a specific quantization table. Quantization of the DCT coefficients is a lossy process, and in this step, noise is added. In this work, we combine IDCT matrix and filter matrix to a new matrix to simplify filtering process to remove noise after IDCT in spatial domain, for each $8{\times}8$ DCT coefficient block, we determine whether this block is edge or homogeneous region. If this block is edge region, we divide this $8{\times}8$ block into four $4{\times}4$ sub-blocks, and do filtering process for sub-blocks which is homogeneous region. By this process, we can remove blocking artifacts efficiently preserving edge regions at the same time.

• Journal of the Korean Society for Railway
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• v.9 no.5 s.36
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• pp.606-611
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• 2006

This paper presents a procedure and an analysis method to evaluate reliability of the Korea high-speed train. The rolling stock system is divided into 6 sub-systems and each subsystem is classified into sub-assemblies. Functional analysis has been conducted to draw reliability block diagrams for the sub-systems. First, failure rates has been calculated for each sub-assembly from the failure data obtained during commissioning tests. Then a reliability block diagram is used to evaluate the MKBF(Mean Kilometers Before Failure) of the sub-systems. Activities to increase reliability have been carried out throughout the test runs and analysis results show that the reliability of the rolling stock system is gradually growing in time.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1123-1130
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• 2005

In this paper, we propose an improved side information processing scheme which is important in the sub-block phase weighting(SPW) method for the peak-to-average power ratio(PAPR) reduction. SPW method is to divide the input OFDM subchannels into several subblocks and to multiply phase weighting with each subblocks, properly for the reduction of the peak power. SPW method is similar to the conventional PTS method when the number of sub-carriers, signal modulation format and the number of subblocks are the same. However, unlike the conventional PTS(Partial Transmit Sequence) and SLM(Selected Mapping) method using many stages of IFFT(Inverse Fast Fourier Transform), SPW method only needs one IFFT. Although PAPR can be reduced by SPW method, complex computation burden still remains. In this paper the flipping algorithm and the full iteration algorithm are used f3r the phase control method. Through the computer simulation, we analyze and discuss the properties and the performance of the suggested method.