• Journal of information and communication convergence engineering
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• 제3권4호
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• pp.187-190
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• 2005

High aspect ratio via-hole etching process has emerged as one of the most crucial means to increase component density for ULSI devices. Because of charge accumulation in via-hole, this sophisticated and important process still hold several problems, such as etching stop and loading effects during fabrication of integrated circuits. Indeed, the concern actually depends on accumulated charge. For monitoring accumulated charge during plasma etching process, charge-up monitoring sensor was fabricated and tested under some plasma conditions. This paper presents a neural network-based technique for analyzing and modeling several electrical performance of plasma charge-up monitoring sensor.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 추계종합학술대회
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• pp.303-306
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• 2005

High aspect ration via-hole etching process has emerged as one of the most crucial means to increase component density for ULSI devices. Because of charge accumulation in via hole, this sophisticated and important process still hold several problems, such as etching stop, loading effects during fabrication of integrated circuits. Indeed, the concern actually depends on accumulated charge. For monitoring accumulated charge during plasma etching process, charge-up monitoring sensor was fabricated and tested under some plasma conditions. This paper presents a neural network-based technique for analyzing and modeling several electrical performance of plasma charge-up monitoring sensor.

• Restorative Dentistry and Endodontics
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• 제14권1호
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• pp.205-210
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• 1989

The purpose of this study was to observe the minim pins of Link plus (which has buttress thread and shoulder stop design) inserted into dentin and the dentin surrounding pin. The gingival walls of class II cavity were prepared with high speed handpiece in molar teeth not elapsed time after teeth were extracted, and pinhole of 2mm in depth was positioned about 1 mm to the dentinoenamel junction and minim pin was inserted with wrench. After initial examination of the specimens, the specimens were sectioned longitudinally and horizontally to the pins with carborundum disc and low speed diamond saw (Isomet Buehler Ltd) All specimens were coated Au of 250-300${\AA}$ in thickness with Ion Sputter JFC 100 and observed under Scanning Electron Microscope (JSM-35) The following results were obtained. 1. The shoulder stop was seated on the enterance of pinhole in gingival wall, and there were the irregular space between the pin and dentin at the enterance to the pin hole and flakes of dentin lifting from the dentin floor. 2. In case of section to pin horizontally or longitudinally, the dentin debris were observed in gap between pin and dentin, and small cracks were often seen in the dentin surrounding minim pins.

• Steel and Composite Structures
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• 제47권2호
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• pp.239-251
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• 2023

The stiffness evaluation of cracked base metal is of great guidance to fatigue crack reinforcement. By carrying out fatigue tests and numerical simulation of typical cracking details in steel box girder, the strain-degradation law of cracked base metal was analyzed and the relationship between base metal stress and its displacement (stiffness) was explored. The feasibility of evaluating the stress of cracked base metal based on the stress field at the crack tip was verified. The results demonstrate that the stiffness of cracked base metal shows the fast-to-slow degradation trend with fatigue cracking and the base metal at 50mm or more behind the crack tip basically lose its bearing capacity. Drilling will further accelerate stiffness degradation with the increase of hole diameters. The base metal stress has a negative linear relation with its displacement (stiffness), The stress of cracked base metal is also related to stress intensity factor and its relative position (distance, included angle) to the crack tip, through which the local stiffness can be effectively evaluated. Since the stiffness is not uniformly distributed along the cracked base metal, the reinforcement patch is suggested to be designed according to the stiffness to avoid excessive reinforcement for the areas incompletely unloaded.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제18권1호
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• pp.233-262
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• 2024

Due to the rapid evolution of vehicular ad hoc networks (VANETs), effective communication and security are now essential components in providing secure and reliable vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) communication. However, due to their dynamic nature and potential threats, VANETs need to have strong security mechanisms. This paper presents a novel approach to improve VANET security by combining the Vehicular Delay-Tolerant Network (VDTN) protocol with the Deep Reinforcement Learning (DRL) technique known as the Twin Delayed Deep Deterministic Policy Gradient (TD3) algorithm. A store-carry-forward method is used by the VDTN protocol to resolve the problems caused by inconsistent connectivity and disturbances in VANETs. The TD3 algorithm is employed for capturing and detecting Worm Hole Attack (WHA) behaviors in VANETs, thereby enhancing security measures. By combining these components, it is possible to create trustworthy and effective communication channels as well as successfully detect and stop rushing attacks inside the VANET. Extensive evaluations and simulations demonstrate the effectiveness of the proposed approach, enhancing both security and communication efficiency.

• Journal of Electrical Engineering and Technology
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• 제6권2호
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• pp.280-283
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• Journal of Electrical Engineering and Technology
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• 제6권2호
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• pp.233-238
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• KIEAE Journal
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• 제7권4호
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• pp.135-140
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• 2007

In this study we settled the trouble of the MgO board of existence by this research. We changed the wooden one of the main ingredient of a board to a perlite and a mineral particle in the aluminum hydroxide group and proceeded with a study to physical character and fire resistance efficiency improvement. The result yellowing phenomenon could be improved and it was possible to reduce size decrease of pin hole and the frequency of occurrence. We found out that the in case of absorbed amount added 5~8% corresponding to the weight decreases the acrylic group emulsion suddenly. So this product is improved with the bending strength and water-resistance. After behavior stop time measurement of a mouse for experiments was measured at the time of a gas harmful effect test, an improved MgO board appeared more highly for an average of 138 seconds compared with a board of existence.

• Transactions on Electrical and Electronic Materials
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• 제6권3호
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• pp.87-90
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• 2005

$SiO_2$ via-hole etching with a high aspect ratio is a key process in fabricating ULSI devices; however, accumulated charge during plasma etching can cause etching stop, micro-loading effects, and charge build-up damage. To alleviate this concern, charge-up damage sensor was fabricated for the ultimate goal of real-time monitoring of accumulated charge. As an effort to reach the ultimate goal, fabricated sensor was used for electrical potential measurements of via holes between two poly-Si electrodes and roughly characterized under various plasma conditions using statistical design of experiment (DOE). The successful identification of potential difference under various plasma conditions not only supports the evidence of potential charge-up damage, but also leads the direction of future study.

• 한국염색가공학회:학술대회논문집
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• 한국염색가공학회 2012년도 제46차 학술발표회
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• pp.95-95
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• 2012

기존의 섬유부자재 생산은 피도물의 접점(고리자국)으로 핀홀(pine-hole)에 녹의 발생하여 제품고급화가 어렵고 작업 시 분진 발생 및 유기물질 배출로 열악한 실정이다. 국내 생산방식은 대부분 위와 같은 방식으로 생산하고 있으나 이는 불량률이 높고 열효율이 떨어지는 단점이 있다. 기존의 저가제품은 중국 및 후발국가의 추격으로 세계시장에서 경쟁력을 잃어가고 있으며 선진국의 경우 섬유부자재의 고급화를 위한 무접점 대형코팅 설비 생산 및 연구개발을 하고 있는 실정이다. 이에 본 연구에서는 무접점 코팅설비의 개발로 피도물에 접점이 없어 녹발생의 원인인 핀홀이 근본적으로 발생하지 않으며, 일괄생산체제를 도입하여 기존의 작업방법 대비 생산성이 향상되고 불량률 및 에너지사용이 감소되며, 또한 원천적으로 분진 및 유기용제 등의 유해물질 배출이 없는 기술을 확보하고자 한다. 개발된 장비의 평가 및 실제 생산현장에서 요구되는 성능을 반영하기 위해 기존 생산설비를 조사하였고, 기존 작업환경에 따른 불량률 및 생산성을 조사하였다. 새로 개발되는 무접점 코팅설비는 기존의 문제점이 보완되며, 에너지 효율 향상 및 작업환경 개선된 One-stop 공정으로 설계하였으며 그 특징은 아래와 같다. 도료 코팅을 위한 파우더 공급 및 제거 공정의 단일화로 생산성을 향상 시키면서 기존보다 분진발생이 거의 없는 도입부 개발 및 밀폐형 코팅부 도입을 통하여 불필요한 열원 낭비를 최소화 시킬 예정이다. 향후 개발된 각 단위 유닛의 최적화를 통한 생산성 향상 및 One-stop 공정에 따른 열효율 개선 및 에너지 사용 절감 효과를 알아보고 피드백하여 최종 개발품에 적용할 예정이다.